Filters








46 Hits in 5.8 sec

Beyond Gbps Turbo decoder on multi-core CPUs

Adrien Cassagne, Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Olivier Aumage, Denis Barthou
2016 2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)  
The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification.  ...  Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency.  ...  Moreover, it exceeds 1 Gbps information throughput on a highend CPU, making multi-core CPU a compelling alternative to GPU for channel decoding processing in cloud-based Random Access Network (RAN) [7  ... 
doi:10.1109/istc.2016.7593092 dblp:conf/istc/CassagneTLGAB16 fatcat:v332yw2acnb3rpqljus5hereue

BigStation

Qing Yang, Xiaoxiao Li, Hongyi Yao, Ji Fang, Kun Tan, Wenjun Hu, Jiansong Zhang, Yongguang Zhang
2013 Computer communication review  
Multi-user multiple-input multiple-output (MU-MIMO) is the latest communication technology that promises to linearly increase the wireless capacity by deploying more antennas on access points (APs).  ...  As a proof of concept, we have built a BigStation prototype based on commodity PC servers and standard Ethernet switches.  ...  As one data point for reference, state-of-the-art multi-core CPUs or DSPs on the market can only process on the order of 50 GOPS per chip.  ... 
doi:10.1145/2534169.2486016 fatcat:tbfryqwygzf6lpd37r67y7e53m

BigStation

Qing Yang, Xiaoxiao Li, Hongyi Yao, Ji Fang, Kun Tan, Wenjun Hu, Jiansong Zhang, Yongguang Zhang
2013 Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM - SIGCOMM '13  
Multi-user multiple-input multiple-output (MU-MIMO) is the latest communication technology that promises to linearly increase the wireless capacity by deploying more antennas on access points (APs).  ...  As a proof of concept, we have built a BigStation prototype based on commodity PC servers and standard Ethernet switches.  ...  As one data point for reference, state-of-the-art multi-core CPUs or DSPs on the market can only process on the order of 50 GOPS per chip.  ... 
doi:10.1145/2486001.2486016 dblp:conf/sigcomm/YangLYFTHZZ13 fatcat:3itkcjdxobhmpppijgjniaf5nq

AMD Fusion APU: Llano

Alexander Branover, Denis Foley, Maurice Steinman
2012 IEEE Micro  
We can apply a separate GPU PDM above and beyond the CPU PDM to the core TDP limit.  ...  Figure 5 . 5 AMD Turbo CORE management of idle compute units: CPU TDP limit ¼ 10 W, resulting in a thermal specification violation (a); one active CPU, power density multiplier (PDM) ¼ 2.0, CPU thermal  ...  Alexander Branover is an Advanced Micro Devices principal staff member involved in system-on-chip (SoC) architecture and power management.  ... 
doi:10.1109/mm.2012.2 fatcat:t7p6vuydp5grlm3vs2crktxdyi

GPU-Based, LDPC Decoding for 5G and Beyond

Chance Tarver, Matthew Tonnemacher, Hao Chen, Jianzhong Zhang, Joseph R. Cavallaro
2021 IEEE Open Journal of Circuits and Systems  
use the cores to work on many codewords simultaneously to target high throughput applications.  ...  With our GPU-based decoder, we measure a best case-latency of 87 μs and a best-case throughput of nearly 4 Gbps using the Titan RTX GPU.  ...  When using 18 cores, they report a max throughput of 5 Gbps. [26] also implements a software-based decoder for OAI. a layered min-sum decoder is adopted using AVX-256 instructions.  ... 
doi:10.1109/ojcas.2020.3042448 fatcat:dxiaef7eijarrlwzwo2h5mb6ri

Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU

Biao Wang, Diego Felix de Souza, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben Juurlink, Aleksandar Ilić, Nuno Roma, Leonel Sousa
2018 Signal processing. Image communication  
Wang). instructions and advanced multi-threading is able to decode 4K UHD video on contemporary desktop CPUs.  ...  Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of 2.2×.  ...  For all decoding configurations (CPU baseline, decoding scheme I and II), the energy consumption per frame is reduced with the increase of CPU cores, but stops reducing approximately beyond 12 cores.  ... 
doi:10.1016/j.image.2017.12.009 fatcat:sn64fkphk5fsflhttlvgykt2zq

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
) and interconnect capabilities and provides an outlook on future trends in terms of mid-term projections about what users may expect in the coming years.  ...  The present report provides a consolidated view on the current and mid-term technologies (2019-2022+) for two important components of an HPC/AI system: computing (general purpose processor and accelerators  ...  the advent of 100 Gbps or multi 100 Gbps networks -also used for network adapters.  ... 
doi:10.5281/zenodo.5534079 fatcat:fdknu7w4mfc5foa4gnmt5vqdna

Redefining Wireless Communication for 6G: Signal Processing Meets Deep Learning with Deep Unfolding [article]

Anu Jagannath, Jithin Jagannath, Tommaso Melodia
2021 arXiv   pre-print
While 5G is still in its infancy, there has been an increased shift in the research community for communication technologies beyond 5G.  ...  ADMM-Net was deployed on an Intel core i7-CPU to exhibit support on a computationally lighter platform with an inference time of ∼ 2.8 ms whereas the semi-definite relaxation (SDR) and DetNet required  ...  The computational efficiency was demonstrated by evaluating TISTA on an Intel Xeon(R) 6-core CPU rather than GPU. Energy efficiency will be a primary factor in designing future 6G radios.  ... 
arXiv:2004.10715v5 fatcat:bsouaizz25eujhsg67ka52pch4

High-throughput, energy-efficient network-on-chip-based hardware accelerators

Turbo Majumder, Partha Pratim Pande, Ananth Kalyanaraman
2013 Sustainable Computing: Informatics and Systems  
Conventional multicore architectures can achieve a limited computational throughput due to the inherent multi-hop nature of the on-chip network infrastructure.  ...  Dedicated centers hosting scientific computing tools on a few high-end servers could rely on hardware accelerator co-processors that contain multiple lightweight custom cores interconnected through an  ...  In all such cases, new data-generation technologies are placing an enormous stress on software tools to perform beyond terascale to peta-and exascale.  ... 
doi:10.1016/j.suscom.2013.01.001 fatcat:3lilgssw75apbbyda7j7iqd72e

Cloud RAN for Mobile Networks—A Technology Overview

Aleksandra Checko, Henrik L. Christiansen, Ying Yan, Lara Scolari, Georgios Kardaras, Michael S. Berger, Lars Dittmann
2015 IEEE Communications Surveys and Tutorials  
This article surveys the state-of-the-art literature on C-RAN. It can serve as a starting point for anyone willing to understand C-RAN architecture and advance the research on C-RAN.  ...  C-RAN enables energy efficient network operation and possible cost savings on baseband resources.  ...  Moreover, we would like to thank colleagues from MTI Radiocomp and DTU Fotonik for all the discussions we had together on the concept of C-RAN.  ... 
doi:10.1109/comst.2014.2355255 fatcat:xiwm3naoj5cx3mgdn22hz24emq

White Paper on Broadband Connectivity in 6G [article]

Nandana Rajatheva, Italo Atzeni, Emil Bjornson, Andre Bourdoux, Stefano Buzzi, Jean-Baptiste Dore, Serhat Erkucuk, Manuel Fuentes, Ke Guan, Yuzhou Hu, Xiaojing Huang, Jari Hulkkonen (+13 others)
2020 arXiv   pre-print
The resource efficiency can be further improved by using various combinations of full-duplex radios, interference management based on rate-splitting, machine-learning-based optimization, coded caching,  ...  The throughput of a single decoder in a 6G device will reach hundreds of Gbps.  ...  Implementation considerations such as area efficiency (in Gbps/mm 2 ), energy efficiency (in Tb/J), and absolute power consumption (W) put huge challenges on code design, decoder architecture, and implementation  ... 
arXiv:2004.14247v1 fatcat:doom4rvlf5aafmtwpdxbyu6dke

Scoring the Terabit/s Goal:Broadband Connectivity in 6G [article]

Nandana Rajatheva, Italo Atzeni, Simon Bicais, Emil Bjornson, Andre Bourdoux, Stefano Buzzi, Carmen D'Andrea, Jean-Baptiste Dore, Serhat Erkucuk, Manuel Fuentes, Ke Guan, Yuzhou Hu (+17 others)
2021 arXiv   pre-print
The throughput of a single decoder in a 6G device will reach hundreds of Gbps.  ...  On the other hand, RS partially decodes the multi-user interference and partially treats it as noise providing a trade-off between fully decoding the interference and fully treating it as noise.  ... 
arXiv:2008.07220v2 fatcat:k4yyvxjguzeqtgewy4bxmnmuo4

Towards efficient resource provisioning in MapReduce

Peter P. Nghiem, Silvia M. Figueira
2016 Journal of Parallel and Distributed Computing  
. • Performance gain decreases quickly beyond the best trade-off point on elbow curve. • Our algorithm for optimal resource provisioning is better than any rules of thumbs. • Use dynamic job profiling  ...  with table of signatures to match optimal task resources. • Efficient task provisioning saves energy and resources for jobs in multi-tenancy. a b s t r a c t The paper presents a novel approach and algorithm  ...  The NameNodes are VM (virtual machines) of 4 cores and 24 GB of RAM each running on Intel Xeon E5-2690 physical hosts of 8 cores and 16 threads with 2.9 GHz base frequency and 3.8 GHz max turbo frequency  ... 
doi:10.1016/j.jpdc.2016.04.001 fatcat:nr2ubgp2p5dm3fyfrv7cbux2r4

A Comprehensive Tutorial on How to Practically Build and Deploy 5G Networks Using Open-Source Software and General-Purpose, Off-the-Shelf Hardware

Sadiq Iqbal, Jehad M. Hamamreh
2021 RS Open Journal on Innovative Communication Technologies  
discuss almost everything related to the history and background of 5G companies and manufacturers, legacy RAN solutions and equipment, different ways and approaches to build a 5G network including RAN, CORE  ...  WISLAB (wislabi.com/solutions) offers solutions for building and deploying fully secure, cloud-based, and low-cost end-to-end 4G/5G networks along with providing consultations on helping companies reduce  ...  The goal of this project is to implement the 5G core network (5GC) defined in 3GPP Release 15 (R15) and beyond. The implementation is based on nextEPC, implementation of 4G EPC R13.  ... 
doi:10.46470/03d8ffbd.4ccb7950 fatcat:3ssp7atjmvamnmzeduc3kv4m4a

A Spectrum Sharing Framework for Intelligent Next Generation Wireless Networks

Felipe A. P. De Figueiredo, Xianjun Jiao, Wei Liu, Ruben Mennes, Irfan Jabandzic, Ingrid Moerman
2018 IEEE Access  
Allied with multi-core enabled Central Processing Units (CPUs), the multi-threaded PHY naturally supports full-duplex communications mode, i.e., one PHY can simultaneously transmit and receive at different  ...  Moreover, each one of the three slot types is self-decodable, i.e., they always carry control data necessary for the receiver to correctly decode the user data section.  ...  His research interests include digital signal processing, digital communications, mobile communications, multi-in multi-out, multicarrier modulations, and field-programmable gate array development. include  ... 
doi:10.1109/access.2018.2875047 fatcat:kaj26tusffeb5fvdecueygukne
« Previous Showing results 1 — 15 out of 46 results