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DEEP

Juergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
This paper introduces the Delaware Enhanced Emulation Platform (DEEP) -a FPGA-based emulation system for hardware/software co-verification of many-core chip architectures.  ...  We also conducted a logic design and integration of a new architectural feature that provides Full/Empty bit fine-grain synchronization for the IBM Cyclops-64 many-core architecture and evaluated its performance  ...  This requires more research in compact parallel tracing formats and better interconnects. ACKNOWLEDGMENTS Our utmost respect goes to Monty Denneau for creating such a great architecture.  ... 
doi:10.1145/1950413.1950438 dblp:conf/fpga/RibutzkaHCG11 fatcat:nmm5lsw5i5e6jgzv32m656krwq

Using emulations to enhance the performance of parallel architectures

B. Obrenic, M.C. Herbordt, A.L. Rosenberg, C.C. Weems
1999 IEEE Transactions on Parallel and Distributed Systems  
AbstractÐWe illustrate the potential of techniques and results from the theory of network emulations to enhance the performance of a parallel architecture.  ...  In order to stress the strength of the approach, we show (via pseudocode) how our emulation techniques can be implemented efficiently even if e operates in strict SIMD mode, with only single-bit masking  ...  A preliminary version of this paper entitled ªAchieving Multigauge Behavior in SIMD Architectures via Emulation,º pp. [186][187][188][189][190][191][192][193][194][195], was presented at the Proc.  ... 
doi:10.1109/71.808155 fatcat:ywjp6sqk5jai7cswtp7gc7xezq

EMUSIM: an integrated emulation and simulation environment for modeling, evaluation, and validation of performance of Cloud computing applications

Rodrigo N. Calheiros, Marco A.S. Netto, César A.F. De Rose, Rajkumar Buyya
2012 Software, Practice & Experience  
In order to better predict service's behavior on Cloud platforms, we developed an integrated architecture that is based on both simulation and emulation.  ...  The proposed architecture, named EMUSIM, automatically extracts information from application behavior via emulation and then uses this information to generate the corresponding simulation model.  ...  parallelism level to p 0 obtained via emulation; 4 c 1 ← closest concurrency level to c 0 obtained via emulation; 5 c 2 ← second closest concurrency level to c 0 obtained via emulation; 6 if (c 0 > c  ... 
doi:10.1002/spe.2124 fatcat:yht5avbvyzb5vck55id7kgmh2m

TANGO: Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation [article]

Karim Djemame and Django Armstrong and Richard Kavanagh and Jean-Christophe Deprez and Ana Juan Ferrer and David Garcia Perez and Rosa Badia and Raul Sirvent and Jorge Ejarque and Yiannis Georgiou
2016 arXiv   pre-print
The paper is concerned with the issue of how software systems actually use Heterogeneous Parallel Architectures (HPAs), with the goal of optimizing power consumption on these resources.  ...  To do so, a reference architecture to support energy efficiency at application construction, deployment, and operation is discussed, as well as its implementation and evaluation plans.  ...  Acknowledgments This work is partly supported by the European Commission under H2020-ICT-20152 contract 687584 -Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation (  ... 
arXiv:1603.01407v1 fatcat:3yjffrybxfbondmjgq5vy5fjd4

CIGAR: Application Partitioning for a CPU/Coprocessor Architecture

John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steve Lumetta, Wen-mei Hwu
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
Examples of how a developer would use CIGAR to partition an application for a heterogeneous CPU/coprocessor environment are demonstrated. 16th International Conference on Parallel Architecture and Compilation  ...  coprocessor execution of these parts, and debug correctness of partitioned execution of the application using emulation.  ...  Future research could leverage performance characteristics tracked using the cycle-accurate simulator to better model CUBA on the emulation platform, providing the developer with both the speed of emulation  ... 
doi:10.1109/pact.2007.4336222 fatcat:gbyzpe3ycvfuzgis4rajbtqamu

GPU virtualization on VMware's hosted I/O architecture

Micah Dowty, Jeremy Sugerman
2009 ACM SIGOPS Operating Systems Review  
We also compare against software rendering, the GPU virtualization in Parallels Desktop 3.0, and the native GPU.  ...  We find that taking advantage of hardware acceleration significantly closes the gap between pure emulation and native, but that different implementations and host graphics stacks show distinct variation  ...  Aaditya Chandrasekhar pioneered our shader translation architecture and continues to advance our Direct3D virtualization.  ... 
doi:10.1145/1618525.1618534 fatcat:tm5aawpxqffpjgaqys2dqzzmom

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems

Michel Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola Celanovic, Srinivas Devadas
2011 2011 IEEE 32nd Real-Time Systems Symposium  
Our real-time hardware emulation for HiL systems is based on a reconfigurable, heterogeneous, multicore processor architecture that emulates power electronics, and includes a circuit compiler that translates  ...  We present the hardware architecture, and describe the process of power electronic circuit compilation.  ...  This approach provides better parallelism and resilience to bank failure. Each bank has separate data and address lines, and the implementation of the bank-based memory is also relatively simple.  ... 
doi:10.1109/rtss.2011.35 dblp:conf/rtss/KinsyKCMCD11 fatcat:p5g4mwqlcbgpvovedevvjpqtyq

Parallel simulation of software defined networks

Dong Jin, David M. Nicol
2013 Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation - SIGSIM-PADS '13  
We leverage our prior work on a hybrid network testbed with a parallel network simulator and a virtual-machine-based emulation system.  ...  architecture for active controllers.  ...  via the OpenFlow protocol.  ... 
doi:10.1145/2486092.2486104 dblp:conf/pads/JinN13 fatcat:6at74bjuybcgffymsgn3lwrnsm

Virtualization - an Answer to Secure Development of Online Experiments

Tomáš Frt'ala, Katarína Žáková
2014 IFAC Proceedings Volumes  
It enables faster execution of guest operation system requests and better utilization of system resources.  ...  The design of the slave server is calculating with the fact that maximum two guest operating systems will run in parallel.  ... 
doi:10.3182/20140824-6-za-1003.02454 fatcat:vs5jmqyacvhzrghynuc5eo7ozm

Parallel Simulation and Virtual-Machine-Based Emulation of Software-Defined Networks

Dong Jin, David M. Nicol
2015 ACM Transactions on Modeling and Computer Simulation  
Parallel simulation and virtual-machine-based emulation of softwaredefined networks. ACM Trans. Model.  ...  In this article, we develop a framework to support OpenFlow-based SDN simulation and distributed emulation, by leveraging our prior work on a hybrid network testbed with a parallel network simulator and  ...  Matthew Caesar for their ideas on uncertaintyaware data plane verification in SDN-based networks and valuable discussions on running simulation/emulation experiments for the case study.  ... 
doi:10.1145/2834116 fatcat:7zuiinif4rfl3mh2laudth24se

A Comparative Study of Heterogeneous Processor Simulators

Shagufta S., Muhammad Aleem, Muhammad Arshad, Muhammad Azhar
2016 International Journal of Computer Applications  
Computer architecture is shifting from multi-core to heterogeneous era. Generally, computer architects practice of software simulation to model and analyze their ideas.  ...  Complex components in the gem5 can be added and removed via this interface [11] . Gem5 simulators's system mode consists two types of modes: System Call and Full system emulations.  ...  The experimental results show that the multi2sim performs better compared to the gem5 and achieves up to 9.4 times better performance results.  ... 
doi:10.5120/ijca2016911316 fatcat:t7532ev45nhu7m3pt4r4fwqjna

Evaluation of the Stretch S6 Hybrid Reconfigurable Embedded CPU Architecture for Power-Efficient Scientific Computing

Thang Viet Huynh, Manfred Mücke, Wilfried N. Gansterer
2012 Procedia Computer Science  
For lower precision number formats, multiple parallel arithmetic units can be implemented.  ...  Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption.  ...  LDX {DP LINPACK, software-emulated via Xtensa ALU}: Software-emulated DP arithmetic via Xtensa ALU. 2. LD1 {DP LINPACK, Xtensa+ISEF (DFMA)}: DAXPY uses extension instruction DFMA. 3.  ... 
doi:10.1016/j.procs.2012.04.021 fatcat:cn6cu3waabacpepdwvd6rb4ruu

Assembling a resolution multiprocessor from interface, programming and distributed processing components

Hamish Taylor
1996 Computer languages  
Prolog programs either explicitly control parallel execution through message passing or would have to rely on program transformation techniques to extract parallelism implicitly.  ...  Widely used, portable, components can be modularly composed into a portable parallel system that displays good resistance to premature obsolescence by software evolution.  ...  evolution and was to be readily available on many parallel architectures.  ... 
doi:10.1016/s0096-0551(96)00013-6 fatcat:ztszoc7v4ja3pj6plxguso55ii

Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

Yangfan Liu, Peng Liu, Yingtao Jiang, Mei Yang, Kejun Wu, Weidong Wang, Qingdong Yao
2010 International journal of electronics (Print)  
The regions may be partitioned in various ways to achieve different objectives, such as better utilisation of resources on each FPGA or better utilisation of the parallel wires 1252 Y.  ...  Figure 7b shows one type of region partition for 4 6 4 mesh-based NoCs, which makes better use of the parallel wires between the middle FPGA and the surrounding FPGAs.  ... 
doi:10.1080/00207217.2010.512017 fatcat:qbrf2q4uujdbfisp7oj3rbpojy

A Fast Network-on-Chip Simulator with QEMU and SystemC

Keita Nakajima, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Hiroaki Takada
2012 2012 Third International Conference on Networking and Computing  
In this work, we have developed a fast simulator of NoC architectures using QEMU and SystemC.  ...  Our simulator is fast because QEMUs run in parallel on a multi-core host computer or even multiple host computers.  ...  Thus, the Syste QEMUs can be executed in parallel on t Our NoC simulator can be executed computers since the SystemC simulato connected via standard TCP sockets.  ... 
doi:10.1109/icnc.2012.55 dblp:conf/ic-nc/NakajimaHTTT12 fatcat:y6u6fz3pdfawrnc67mydssjz3i
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