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Power-Efficient Spilling Techniques for Chip Multiprocessors [chapter]

Enric Herrero, José González, Ramon Canal
2010 Lecture Notes in Computer Science  
To optimize the usage of on-chip memory space and reduce off-chip traffic several techniques have proposed to use the N-chance forwarding mechanism, a solution for distributing unused cache space in chip  ...  Compared to traditional Spilling, our Distance-Aware Spilling technique provides an energy efficiency improvement (MIPS 3 /W) of 16% on average, and a reduction of the network usage of 14% in a ring configuration  ...  Acknowledgements This work has been supported by the Generalitat de Catalunya under grant 2009SGR1250 and the Spanish Ministry of Education and Science under grant TIN2007-61763.  ... 
doi:10.1007/978-3-642-15277-1_25 fatcat:rpovf4sbvrgwjdmrmremxdqc7u

Temperature-Aware On-Chip Networks

Li Shang, L. Peh, A. Kumar, N.K. Jha
2006 IEEE Micro  
network traffic traces; and Howard Chen of IBM for helping us validate our thermal model.  ...  Acknowledgments We thank Kevin Skadron and Wei Huang of the University of Virginia for their help in our understanding of HotSpot; the MIT Raw group, especially Michael B.  ...  The result can be an unbalanced traffic distribution that introduces new thermal hotspots.  ... 
doi:10.1109/mm.2006.23 fatcat:xojbhetblbaxzjt6of7u6wgpfa

DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks [article]

Ebadollah Taheri and Sudeep Pasricha and Mahdi Nikdast
2021 arXiv   pre-print
Unfortunately, existing fault-tolerant routing techniques proposed for 2D and 3D on-chip networks cannot be applied to chiplet networks.  ...  Compared to the state-of-the-art routing algorithms in 2.5D chiplet systems, our simulation results show that DeFT improves network reachability by up to 75% with a fault rate of up to 25% and reduces  ...  The distribution of VC utilization for synthetic traffic patterns are shown in Fig. 5 .  ... 
arXiv:2112.09234v1 fatcat:wtpb4zpa65h3bpjtbuz732rs2m

Flattened Butterfly Topology for On-Chip Networks

John Kim, James Balfour, William Dally
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks.  ...  With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently.  ...  In this paper, we describe how the flattened butterfly topology [15] for on-chip networks use concentration as well as high-radix routers to reduce the diameter of the network to improve cost-efficiency  ... 
doi:10.1109/micro.2007.29 dblp:conf/micro/KimBD07 fatcat:q7bbwgngnzcohoibbypf4ogb6u

Flattened Butterfly Topology for On-Chip Networks

John Kim, James Balfour, William Dally
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks.  ...  With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently.  ...  In this paper, we describe how the flattened butterfly topology [15] for on-chip networks use concentration as well as high-radix routers to reduce the diameter of the network to improve cost-efficiency  ... 
doi:10.1109/micro.2007.4408254 fatcat:o5msxpo2arefvhcumlfbx3jvfi

Flattened Butterfly Topology for On-Chip Networks

J. Kim, J. Balfour, W.J. Dally
2007 IEEE computer architecture letters  
In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks.  ...  With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently.  ...  In this paper, we describe how the flattened butterfly topology [15] for on-chip networks use concentration as well as high-radix routers to reduce the diameter of the network to improve cost-efficiency  ... 
doi:10.1109/l-ca.2007.10 fatcat:j3djnszom5bdxcse5kwkqkdssy

Achieving lightweight multicast in asynchronous networks-on-chip using local speculation

Kshitij Bhardwaj, Steven M. Nowick
2016 Proceedings of the 53rd Annual Design Automation Conference on - DAC '16  
Interestingly, similar improvements are also shown for unicast. Finally, another benefit is to reduce the address field size in multicast packets.  ...  A novel strategy, local speculation, is introduced, where a subset of switches are speculative and always broadcast.  ...  Most of the NoC research has been devoted to improving performance, power and fault-tolerance for unicast (i.e. one-to-one) traffic.  ... 
doi:10.1145/2897937.2897978 dblp:conf/dac/BhardwajN16 fatcat:gawxtqv2z5fr3gacavmwssmu2u

Spectral efficiency and energy consumption tradeoffs for reconfigurable devices in heterogeneous wireless systems

Rahul Amin, Jim Martin, Ahmed Eltawil, Amr Hussien
2012 2012 IEEE Wireless Communications and Networking Conference (WCNC)  
In this paper, for such an integrated heterogeneous wireless system, we show the possible gains in spectral efficiency at the cost of increased energy consumption for an unbalanced heterogeneous wireless  ...  (615%) for users supporting elastic traffic.  ...  Another relevant standard, IEEE P1900.4, defines building blocks for enabling coordinated network-device distributed decision making, which will aid in the optimization of radio resource usage, including  ... 
doi:10.1109/wcnc.2012.6214057 dblp:conf/wcnc/AminMEH12 fatcat:g62h7ztrrjglhom4ieptjx675i

CONNECT

Michael K. Papamichael, James C. Hoe
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
In this paper, we present a Network-on-Chip (NoC) design study from the mindset of NoC as a synthesizable infrastructural element to support emerging System-on-Chip (SoC) applications on FPGAs.  ...  For example, in the case of a 4x4 mesh configuration evaluated using a set of synthetic traffic patterns, we obtain comparable or better performance than the state-of-the-art NoC while reducing logic resource  ...  In all cases the unbalanced traffic pattern, which consists of mostly local traffic, increases the saturation throughput across all networks, which is expected for the mesh topology that performs better  ... 
doi:10.1145/2145694.2145703 dblp:conf/fpga/PapamichaelH12 fatcat:cenpus57ovf4jaq6mrsajdbdla

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance.  ...  The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSERC and the NSF.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

Exploring partitioning methods for multicast in 3D bufferless Network on Chip

Chaoyun Yao, Chaochao Feng, Minxuan Zhang, Wei Guo, Shouzhong Zhu, Shaojun Wei
2015 IEICE Electronics Express  
network on chip.  ...  In this paper, we first propose two multicast partitioning methods named TBP (two block partitioning) and LBP (layer block partitioning), each of which has a different level of efficiency in 3D bufferless  ...  Though buffers can improve the bandwidth efficiency of the network, they also consume much energy and chip area [10] .  ... 
doi:10.1587/elex.12.20150802 fatcat:tgixb3gllfgm7neikplosu5uoq

SCOC: High-radix switches made of bufferless clos networks

Nikolaos Chrysos, Cyriel Minkenberg, Mark Rudquist, Claude Basso, Brian Vanderpool
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
In this first incarnation, SCOC is used at the spines of a server-rack, fat-tree network.  ...  In today's datacenters handling big data and for exascale computers of tomorrow, there is a pressing need for highradix switches to economically and efficiently unify the computing and storage resources  ...  SCOC also presents a competent alternative to (low-performance) mesh networks and to (hard-to-scale) crossbars for on-chip networks used in chip multiprocessors.  ... 
doi:10.1109/hpca.2015.7056050 dblp:conf/hpca/ChrysosMRBV15 fatcat:duy2jjvdhzdjfo3x3spzoslfie

A flexible data to L2 cache mapping approach for future multicore processors

Lei Jin, Hyunjin Lee, Sangyeun Cho
2006 Proceedings of the 2006 workshop on Memory system performance and correctness - MSPC '06  
L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for high program performance and to reduce on-chip network traffic and related power consumption  ...  This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores.  ...  In terms of network traffic, SP40 cuts down the on-chip network traffic by at least 50% in all the programs, compared with SL.  ... 
doi:10.1145/1178597.1178613 dblp:conf/ACMmsp/JinLC06 fatcat:3puyalgmtvao7fzvbm2yzigqzm

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program)

Madeleine Glick, Nathan Abrams, Qixiang Cheng, Min Yee Teh, Yu-Han Hung, Oscar Jimenez, Songtao Liu, Yoshitomo Okawachi, Michal Lipson, Alexander Gaeta, Keren Bergman, Leif Johansson (+7 others)
2020 Journal of Optical Communications and Networking  
In phase 1 of the program, the PINE system architecture demonstrated an average factor of 2.2× improvement in transactions/joule across a diverse set of HPC and datacenter applications.  ...  efficiency improvements than can be achieved through link energy efficiency alone.  ...  CONCLUSION Energy-optimized optical link technology is essential for improving the energy efficiency of interconnects for datacenters and HPC.  ... 
doi:10.1364/jocn.402788 fatcat:evcrlkdyjfeunoy6fhh7aagjdy

A Linguistic Study of Speech Comprehension and Production in Aphasic Speakers

2021 Qalaai Zanist Scientific Journal  
Distributed systems are designed separately from the core network. There are different kinds of distributed systems such as peer-to-peer (P2P) networks, groups, grids, distributed storage systems.  ...  This paper reviews the impact of the distributed-memory parallel processing approach on performance-enhancing of multicomputer-  ...  Localization is one of the major challenges encountered in wireless sensor networks, especially in the non-attendance of such GPS installation equipment.  ... 
doi:10.25212/lfu.qzj.6.4.45 fatcat:4zq7bvup5zfqjm6xmnv774bsui
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