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Vertical benchmarks for CAD

Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
More effective than componentbased CAD benchmarks, vertical benchmarks enable quantitative comparison of CAD techniques within or across design flows.  ...  This work describes the notion of vertical benchmarks and presents our benchmark, which is based on a commercial DSP, by comparing two alternative design flows.  ...  Using a vertical benchmark, the impact of CAD techniques can be quantified in terms of system-level performance and Performance Analysis Simulation Physical Design Vertical Benchmark area, rather than  ... 
doi:10.1145/309847.309969 dblp:conf/dac/InacioSNRTTK99 fatcat:62lpdvsyczhvnhlhyhpnxwsbfe

Advances in the Form-finding of Structural Membranes

Benedikt Philipp, Roland Wüchner, Kai-Uwe Bletzinger
2016 Procedia Engineering  
and preparation of the model, but also allows for smooth and close interaction between design and analysis, which is of crucial importance in membrane design.  ...  Selected benchmark examples show the accuracy and robustness of the developed method, assessed against analytical solutions if applicable.  ...  Prototypic applications for the form-finding and structural analysis of tensile membranes with IBRA Two more complete applications shall highlight the ease of modelling and the potential of the presented  ... 
doi:10.1016/j.proeng.2016.08.036 fatcat:neozi2q3qbg4zigwpoipmvowsu

Titan: Enabling large and complex benchmarks in academic CAD

Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz
2013 2013 23rd International Conference on Field programmable Logic and Applications  
Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures.  ...  Using the Titan23 benchmarks and a detailed model of Altera's Stratix IV architecture we compared the performance and quality of VPR and Quartus II targeting the same architecture.  ...  We are grateful to the following organizations and individuals for providing benchmark circuits: Altera, Braiden Brousseau, Deming Chen, Jason Cong, George Constinides, Zefu Dai, Joseph Garvey, IWLS2005  ... 
doi:10.1109/fpl.2013.6645503 dblp:conf/fpl/MurrayWLLB13 fatcat:kuzeoiuhqnhm7foai5p43mkpsa

CADS: Core-Aware Dynamic Scheduler for Multicore Memory Controllers [article]

Eduardo Olmedo Sanchez, Xian-He Sun
2019 arXiv   pre-print
Using CADS policy, we achieve 20% better cycles per instruction (CPI) in running memory intensive and compute intensive PARSEC parallel benchmarks simultaneously, and 16% better CPI with SPEC 2006 benchmarks  ...  We introduce Core-Aware Dynamic Scheduler (CADS) for multicore memory controller. CADS uses Reinforcement Learning (RL) to alter its scheduling strategy dynamically at runtime.  ...  SPEC CPU2006 benchmarks are widely used benchmarks for testing any component of computer architecture research. It is a suite based on current scientific and engineering applications.  ... 
arXiv:1907.07776v1 fatcat:vvrjpymdxvb7dcrdmzveu75hoe

SCUT-AutoALP: A Diverse Benchmark Dataset for Automatic Architectural Layout Parsing

Yubo LIU, Yangting LAI, Jianyong CHEN, Lingyu LIANG, Qiaoming DENG
2020 IEICE transactions on information and systems  
To tackle these problems, many learning-based methods were proposed, and benchmark dataset become one of the essential elements for the data-driven AutoALP.  ...  The results verify the effectiveness and indicate the potential applications of SCUT-AutoALP.  ...  Benchmark Analysis: We analyze the samples and labels of SCUT-AutoALP statistically, and visualize some properties of SCUT-AutoALP. 3.  ... 
doi:10.1587/transinf.2020edl8076 fatcat:sjcwlwaynngarb7vpxzyip5t5q

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain

Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen
2010 ACM Transactions on Design Automation of Electronic Systems  
Also, we show how an academic FPGA framework, VPR 5.0, that has been updated for power estimates can be used to estimates the power consumption of different FPGA architectures and an open-source CAD flow  ...  We present the GroundHog 2009 benchmarking suite that evaluates the power consumption of reconfigurable technology for applications targeting the mobile computing domain.  ...  architectures and applications.  ... 
doi:10.1145/1698759.1698764 fatcat:3rhh6i7xprgz3mrtsg2ntiris4

CAD-based interface programs for fusion neutron transport simulation

Y. Wu
2009 Fusion engineering and design  
This paper introduces the main functions of the three interface programs and a benchmark test based on the ITER model.  ...  Describing and verifying of the models for three-dimensional (3D) neutron transport simulation based on Monte Carlo (MC), discrete ordinates (S N ) and MC-S N coupled methods are time-consuming and errorprone  ...  Testing and analysis In order to test the capability of the above three programs for complex fusion application, the benchmarks have been performed based on the complex ITER geometric model.  ... 
doi:10.1016/j.fusengdes.2008.12.041 fatcat:s2yvid4g3vcarp27ya65vrzxpi

Symbiflow & VPR: An Open-Source Design Flow for Commercial and Novel FPGAs

Kevin E. Murray, Tim Ansell, Keith Rothman, Allessandro Comodi, Mohamed Elgammal, Vaughn Betz
2020 IEEE Micro  
While challenges remain, we believe this approach makes the development of novel and commercial FPGA architectures faster and more accessible.  ...  Furthermore, it provides a path forward for industry, academia, and the opensource community to collaborate and combine their resources to advance FPGA technology.  ...  Wang for assistance collecting benchmark data, as well as the numerous community members who have contributed to the development of VPR and Symbiflow through writing documentation, filling bugs, and submitting  ... 
doi:10.1109/mm.2020.2998435 fatcat:q4h7bjbtbbgnjjrvrzsnwo2nwi

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Jin Hee Kim, Jason H. Anderson
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics.  ...  The opensource Verilog-to-Routing (VTR) FPGA architecture evaluation framework [1] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model.  ...  the application benchmark in a range of architectures.  ... 
doi:10.1109/fpl.2015.7293955 dblp:conf/fpl/KimA15 fatcat:wrsq6lssqvbyvbu4gr7wbuuc6m

Assessment of conformance and interoperability testing methods used for construction industry product models

Robert Lipman, Mark Palmer, Sebastian Palacios
2011 Automation in Construction  
Conformance testing methodologies, with varying degrees of rigor, have been developed and applied to ensure interoperability across product modeling software applications in other engineering and industry  ...  This paper presents a review and assessment of conformance and interoperability testing methods for product data models used in the construction industry.  ...  The assumption is that CAD A and CAD B are similar types of design systems, such as, architectural or structural.  ... 
doi:10.1016/j.autcon.2010.11.011 fatcat:r5c7jkt7knf7tm4wlc3bj4nim4

FPGA global routing architecture optimization using a multicommodity flow approach

Yuanfang Hu, Yi Zhu, Michael B. Taylor, Chung-Kuan Cheng
2007 2007 25th International Conference on Computer Design  
a set of seven benchmark circuits.  ...  This paper presents an improved MCF model based CAD flow that performs aggressive optimizations, such as topology and wire style optimizations, to reduce the energy and switch area of FPGA global routing  ...  Mike Hutton at Altera Crop. for his valuable discussion on the original idea of the work in this paper. We also thank California MICRO funding and the support of Altera.  ... 
doi:10.1109/iccd.2007.4601893 dblp:conf/iccd/HuZTC07 fatcat:gasvqkpborfcrpkagbicfgy6cy

FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI
2013 IEICE transactions on information and systems  
VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons.  ...  First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming.  ...  Acknowledgments This work was supported by the VLSI Design and Education Center (VDEC) of the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design System, Inc., and Mentor Graphics,  ... 
doi:10.1587/transinf.e96.d.1602 fatcat:quem56ufirhpxma7ts23owiz7y

Exploration and Customization of FPGA-Based Soft Processors

Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
of soft processors for specific applications.  ...  Through these two techniques, we can improve the performance-per-area of a soft processor for a specific application by an average of 25%.  ...  We present methods for verifying the processors, employing FPGA CAD tools, and measuring and comparing soft processors. Also, we discuss the benchmark applications that we use to do so. A.  ... 
doi:10.1109/tcad.2006.887921 fatcat:gfpeul3d6bbxth65lanhaftlzi

Performance Evaluation of Deep Learning-Based Prostate Cancer Screening Methods in Histopathological Images: Measuring the Impact of the Model's Complexity on Its Processing Speed

Lourdes Duran-Lopez, Juan P. Dominguez-Morales, Antonio Rios-Navarro, Daniel Gutierrez-Galan, Angel Jimenez-Fernandez, Saturnino Vicente-Diaz, Alejandro Linares-Barranco
2021 Sensors  
In this work, we measured the performance of current state-of-the-art models for PCa detection with a novel benchmark and compared the results with PROMETEO, a custom architecture that we proposed.  ...  The results of the comprehensive comparison show that using dedicated models for specific applications could be of great importance in the future.  ...  This procedure has been widely used in order to develop CAD systems in this field. Recently, many researchers have investigated the application of CAD systems to the diagnosis of PCa in WSIs.  ... 
doi:10.3390/s21041122 pmid:33562753 pmcid:PMC7915373 fatcat:7zx3svhj45eklai7j35zdixn4y

VTR 7.0

Jason Luu, Nooruddin Ahmed, Kenneth B. Kent, Jason Anderson, Jonathan Rose, Vaughn Betz, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr (+2 others)
2014 ACM Transactions on Reconfigurable Technology and Systems  
Finally, we show that while this version of VTR supports new and complex features, it has a 1.5× compile time speed-up for simple architectures and a 6× speed-up for complex architectures compared to the  ...  VTR now supports designs with multiple clocks in both timing analysis and optimization.  ...  ACKNOWLEDGMENTS The authors would like to thank the numerous researchers who have helped create and enhance the VPR, ODIN II and ABC CAD tools over many years.  ... 
doi:10.1145/2617593 fatcat:rqrma7exgfdzxf3ml5xysnnzii
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