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Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints [chapter]

Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
2000 Lecture Notes in Computer Science  
Partitioning of the design is done under multiple constraints -interconnections and device areas of the reconfigurable architecture, and the latency of the design.  ...  A partitioning and synthesis framework was developed, with the FMPAR behavioral partitioner at the front-end and various synthesis phases (High-Level, Logic and Layout) at the back end.  ...  Summary This paper presents a framework for multi-FPGA partitioning of behavioral designs and their synthesis onto reconfigurable boards.  ... 
doi:10.1007/3-540-45591-4_127 fatcat:ncctvs44efd33ia4bdi3bhldfa

Target architecture oriented high-level synthesis for multi-FPGA based emulation

Oliver Bringmann, Carsten Menn, Wolfgang Rosenstiel
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems.  ...  The goal is to synthesize a prototype with maximal performance under the given area and interconnection constraints of the target architecture.  ...  Synthesis flow As mentioned before, the objective is to incorporate circuit partitioning and high-level synthesis based on an extended interconnection cost model for a given multiplechip target architecture  ... 
doi:10.1145/343647.343790 fatcat:gt26qspijze6xpyyyy6l3ct5d4

Evaluation of NoC on multi-FPGA interconnection using GTX transceiver

Atef Dorai, Olivier Sentieys, Helene Dubois
2017 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
The simulation results show that the proposed architecture provides low area consumption and latencies under different traffic patterns.  ...  Multi-FPGA platforms are very popular today for pre-silicon verification of complex designs due to their low cost and high speed.  ...  The flow generation of a NoC on multi-FPGA requires passing through several stages as synthesis and partitioning of the NoC on multi-FPGA.  ... 
doi:10.1109/icecs.2017.8292007 dblp:conf/icecsys/DoraiSD17 fatcat:3nhtebthtncxdisg2fyuslojte

sFPGA — A scalable switch based FPGA architecture and design methodology

Shakith Fernando, Xiaolei Chen, Yajun Ha
2008 2008 International Conference on Field Programmable Logic and Applications  
In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and Network-on-Chip.  ...  A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed.  ...  More significantly, given enough wiring layers, MoT interconnection networks only require O(N ) area. A complementary interconnect architecture, ToM, for FPGA, is analyzed in [2] .  ... 
doi:10.1109/fpl.2008.4629914 dblp:conf/fpl/FernandoCH08 fatcat:qyaz2fghhbb4ncruz7y6aqurju

DART: A Programmable Architecture for NoC Simulation on FPGAs

2014 IEEE transactions on computers  
To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture.  ...  The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems  ...  Acknowledgements This research was supported by the Natural Science and Engineering Research Council (NSERC). We thank Jason Anderson and Andreas Moshovos for their feedback on this work.  ... 
doi:10.1109/tc.2012.121 fatcat:utp3dgsyrjfovogo2j3ea5ghr4

DART

Danyao Wang, Natalie Enright Jerger, J. Gregory Steffan
2011 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip - NOCS '11  
To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture.  ...  The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems  ...  Acknowledgements This research was supported by the Natural Science and Engineering Research Council (NSERC). We thank Jason Anderson and Andreas Moshovos for their feedback on this work.  ... 
doi:10.1145/1999946.1999970 dblp:conf/nocs/WangJS11 fatcat:pdsncvrtsbdwxp5udj5vhr6hi4

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Deming Chen, Jason Cong, Yiping Fan, Lu Wan
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization.  ...  Index Terms-Behavioral synthesis, field-programmable gate array (FPGA), interconnect, power optimization.  ...  High-level synthesis for a multi-FPGA system is done in [14] .  ... 
doi:10.1109/tvlsi.2009.2013353 fatcat:vv3ymb26wzddbnuzveoed76vem

Architecture and synthesis for multi-cycle communication

Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
2003 Proceedings of the 2003 international symposium on Physical design - ISPD '03  
This requires the consideration of multi-cycle communication during architectural & behavioral synthesis. [10] proposed an architectural synthesis approach which incorporates a performance-driven placement  ...  For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles.  ...  This step also generates floorplan information and multi-cycle constraints for RDR synthesis flows.  ... 
doi:10.1145/640000.640040 dblp:conf/ispd/CongFYZ03 fatcat:67jz2i2j5fc6tcg7gy3i6pwhgi

Architecture and synthesis for multi-cycle communication

Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
2003 Proceedings of the 2003 international symposium on Physical design - ISPD '03  
This requires the consideration of multi-cycle communication during architectural & behavioral synthesis. [10] proposed an architectural synthesis approach which incorporates a performance-driven placement  ...  For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles.  ...  This step also generates floorplan information and multi-cycle constraints for RDR synthesis flows.  ... 
doi:10.1145/640038.640040 fatcat:j27rwnrupfa75jhslq2iri3rr4

Efficient resource arbitration in reconfigurable computing environments

Iyad Ouaiss, Ranga Vemuri
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
In a multi-FPGA synthesis system, ideally the designer has only an abstract view of the board architecture.  ...  This abstract modeling of the underlying reconfigurable computer poses complex challenges to the synthesis and partitioning tools.  ...  These multi-FPGA reconfigurable computers eased the area constraint but introduced design complexities.  ... 
doi:10.1145/343647.343856 fatcat:dtxelwyvkngxdgqriaapgtn5ru

Acceleration of pedestrian detection algorithm on novel C2RTL HW/SW Co-design platform

Yihao Zhu, Yongpan Liu, Daming Zhang, Shuangchen Li, Pei Zhang, Tedd Hadley
2010 The 2010 International Conference on Green Circuits and Systems  
Considering the performance and flexibility of hardware/ software co-design architecture (CPU+FPGA), it is feasible to implement these algorithms on such platforms.  ...  In this paper, we present a popular template-based detection algorithm on such a novel platform which including an ATOM processor and a FPGA-based accelerator, and designed by a novel C2RTL automatic design  ...  By profiling the performance, we proposed a multi-accelerator architecture to improve performance and discussed tradeoffs between performance and area for number of accelerators.  ... 
doi:10.1109/icgcs.2010.5542990 fatcat:2dvtfb7anbbklef3fnqpcuboda

Memory Synthesis for FPGA-Based Reconfigurable Computers [chapter]

Amit Kasat, Iyad Ouaiss, Ranga Vemuri
2001 Lecture Notes in Computer Science  
I enjoyed and learnt a lot while working in close coordination with him. He was always present for help and suggestions.  ...  It was great to work with Madhu and Siva for the review meeting. It was nice to have friends like Vijay, Sairavi, Jawad and Manish.  ...  Acknowledgments First and foremost, I would like to thank my advisor Dr. Ranga Vemuri. Working with him was a great learning opportunity for me.  ... 
doi:10.1007/3-540-44687-7_8 fatcat:ggjaodw6wngkzkts6pcpq6kqgy

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Asmeen Kashif, Mohammed A. S. Khalid
2016 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)  
Thus, the choice of off-chip interconnection type at very high data rates can determine the latency, bandwidth, area and cost constraints in an MFS.  ...  Multi-FPGA System Constraints Pin Limitation Problem The first constraint of an MFS is the limited number of I/O pins.  ... 
doi:10.1109/mwscas.2016.7869975 dblp:conf/mwscas/KashifK16 fatcat:hgpls6pryvfvpnsbwnvxup6o34

Challenges and opportunities of ESL design automation

Zhiru Zhang, Deming Chen
2012 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology  
This paper identifies a set of key challenges in ESL design automation with major focus on high-level synthesis (HLS).  ...  Such an improvement in efficiency is much needed for design in the deep submicron era.  ...  As technology advances, the area and power of multiplexers and interconnects have by far outweighed the area and power of functional units and registers especially for FPGA architectures.  ... 
doi:10.1109/icsict.2012.6467670 fatcat:6cium5rwsjhsteh46ip6bnbxjy

An integrated and automated memory optimization flow for FPGA behavioral synthesis

Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
2012 17th Asia and South Pacific Design Automation Conference  
In this paper we integrate data reuse, loop pipelining, memory partitioning, and memory merging into an automated optimization flow (AMO) for FPGA behavioral synthesis.  ...  Experimental results on Xilinx Virtex-6 FPGAs show that our integrated approach can gain an average 5.8x throughput and 4.55x latency improvement compared to the approach without memory partitioning.  ...  This work was supported in part by the Semiconductor Research Corporation (SRC) under Contract 2009-TJ-1879, and in part by the National Science Foundation (NSF) under the Expeditions in Computing Program  ... 
doi:10.1109/aspdac.2012.6164955 dblp:conf/aspdac/WangZCC12 fatcat:utp3igrbw5dvjd6lwsszjlhgxy
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