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BOOM: Enabling mobile memory based low-power server DIMMs

Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
In this paper, we exploit the low-power nature of another high volume memory component-mobile DRAM-while improving its bandwidth and reliability shortcomings with a new DIMM architecture.  ...  Conventional and recently-proposed server memory techniques can satisfy these requirements, but at the cost of significantly increased memory power, a key constraint for future memory systems.  ...  ., ×16) at low frequency. Together, they enable mobile memory devices in servers, drastically saving memory power. 3. We evaluate BOOM using cycle-based simulations.  ... 
doi:10.1109/isca.2012.6237003 dblp:conf/isca/YoonCMR12 fatcat:d2qmjq2z3rg3zcdccewf5l22wi

BOOM

Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan
2012 SIGARCH Computer Architecture News  
In this paper, we exploit the low-power nature of another high volume memory component-mobile DRAM-while improving its bandwidth and reliability shortcomings with a new DIMM architecture.  ...  Conventional and recently-proposed server memory techniques can satisfy these requirements, but at the cost of significantly increased memory power, a key constraint for future memory systems.  ...  ., ×16) at low frequency. Together, they enable mobile memory devices in servers, drastically saving memory power. 3. We evaluate BOOM using cycle-based simulations.  ... 
doi:10.1145/2366231.2337163 fatcat:qgufjw7lazadbn7uqn4rogpzkq

CACTI-IO

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2012 Proceedings of the International Conference on Computer-Aided Design - ICCAD '12  
We describe CACTI-IO, an extension to CACTI [4] that includes power, area and timing models for the IO and PHY of the off-chip memory interface for various server and mobile configurations.  ...  , number of ranks, memory data width and off-chip bus frequency, especially for novel buffer-based topologies, and (iii) enable architects to quickly explore new interconnect technologies, including 3-  ...  As servers become more sensitive to memory subsystem power, BOOM provides a valuable means for use of mobile DRAM to achieve better power efficiency while still meeting server performance requirements  ... 
doi:10.1145/2429384.2429446 dblp:conf/iccad/JouppiKMS12 fatcat:6l66t72mrjehxon3yee3l4zrbi

MIMS: Towards a Message Interface Based Memory System

Li-Cheng Chen, Ming-Yu Chen, Yuan Ruan, Yong-Bing Huang, Ze-Han Cui, Tian-Yue Lu, Yun-Gang Bao
2014 Journal of Computer Science and Technology  
In this paper, we argue that a message-based interface should be adopted to replace the traditional bus-based interface in memory system.  ...  A novel message interface based memory system (MIMS) is proposed. The key innovation of MIMS is that processor and memory system communicate through a universal and flexible message interface.  ...  With a similar idea, BOOM [33] adds a buffer chip between the fast DDR3 memory bus and wide internal bus, which enables the use of low-frequency mobile DRAM devices, thus BOOM could efficiently reduce  ... 
doi:10.1007/s11390-014-1428-7 fatcat:ywlupx7r2vhsnngdh3uozw4omy

D5.1: Market and Technology Watch Report Year1

Nico Sanna, Aris Sotiropoulos
2018 Zenodo  
Among the most powerful HPC systems, NVIDIA GPUs appear to be the preferred accelerator followed by Xeon Phi, but future trends will drastically change after the announcement of its withdrawal by Intel  ...  In summary, the TOP500 list is still dominated by systems based in China, but Japan is emerging in the Green500 list where the first EU system is ranked #10.  ...  While the former is meant for extreme low-power, low budget applications, the latter is notably based on a novel, flexible design.  ... 
doi:10.5281/zenodo.6805965 fatcat:656msfaojzhfznp4kwta7jkyyy

COREnect D3.3. Initial COREnect industry roadmap [article]

AUSTRALO
2021 Zenodo  
Low-power, no-charge based memory The stand-alone market is currently dominated and driven by 3D NAND-Flash.  ...  3D packaging technology  real-time  latency  specialized hardware-based AI accelerators o low-power technologies for AI on value added technologies o low-power embedded Non-Volatile Memory (eNVM)   ... 
doi:10.5281/zenodo.5075317 fatcat:ww7icphzfjcdjlxbsbo2qekghy

D5.3: Updated Best Practices for HPC Procurement and Infrastructure

Andreas Johansson
2014 Zenodo  
It has also analysed the current state of the art in cooling and power efficient operating of HPC infrastructure.  ...  Task 2 – Best practices for designing and operating power efficient HPC centre infrastructures – has continued the production of white papers which explore specific topics related to HPC data centre design  ...  Major vendors are: The most promising medium for the future is the NAND based memory in the SSD or PCIe or DIMMs format.  ... 
doi:10.5281/zenodo.6572433 fatcat:cwiqrgf33jajjjvhubky4f6rau

An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks

Jaco Hofmann
2019
The technology has been employed initially in low powered mobile devices [109] , and is nowadays also used in enterprise storage [35] .  ...  The board comes with a Xilinx Virtex 7 FPGA and 8 GB of memory across two DDR3-SDRAM DIMM modules.  ... 
doi:10.25534/tuprints-00010355 fatcat:4567mf3vvjbvxilumnmkbmqwgu

Information Systems for Business and Beyond

David Bourgeois, Saylor
unpublished
But aggregated, indexed, and organized together into a database, data can become a powerful tool for businesses.  ...  RAM is generally installed in a personal computer through the use of a dual-inline memory module (DIMM). The type of DIMM accepted into a computer is dependent upon the motherboard.  ...  As described by Moore's Law, the amount of memory and speeds of DIMMs have increased dramatically over the years.  ... 
fatcat:zeh6zm6dcre3zishqfi2rvlo2a

Aspects of Code Generation and Data Transfer Techniques for Modern Parallel Architectures

Manuel Mohr
2018
This chapter is based on publications that are joint Acknowledgments. This part of this dissertation is joint work with  ...  In power-constrained contexts, such as mobile computing, (partially) giving up cache coherence can enable more aggressive power savings.  ...  This would enable more powerful instructions to implement RTGs that also allow value duplication.  ... 
doi:10.5445/ir/1000085052 fatcat:5omn7z2o3jhtra5wcxj4k3slmu