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BEE2 A High-End Reconfigurable Computing System
2005
IEEE Design & Test of Computers
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BEE2: A High-End Reconfigurable Computing System The BEE2 project is developing a reusable, modular, and scalable framework for designing high-end reconfigurable computers, including a processingmodule ...
A HIGH-END RECONFIGURABLE COMPUTER (HERC) is a machine with supercomputer-level performance configured on a per-problem basis to match the structure of the algorithm and data flow of a computing task. ...
His research interests include the design and application of reconfigurable computing systems, parallel computing architectures, and VLSI design. ...
doi:10.1109/mdt.2005.30
fatcat:mbmzueobdbdqteji63dnf3kkjy
The design and applications of BEE2: A high end reconfigurable computing system
2005
2005 IEEE Hot Chips XVII Symposium (HCS)
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High-End Reconfigurable Computer (HERC) • A computer with supercomputer-like performance, based solely on FPGAs and/or other reconfigurable devices as the processing elements. ...
ASIC
August 16th, 2005
EECS, UC Berkeley
13
BEE2 system design philosophy
• Compute-by-the-yard
-Modular computing resource
-Flexible interconnect architecture
-On-demand reconfiguration of ...
doi:10.1109/hotchips.2005.7476601
fatcat:jivx5rygyng2tenoaadchrg7te
Radio Testbeds Using BEE2
2007
Asilomar Conference on Signals, Systems and Computers. Conference Record
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The BEE2 programming and debugging capabilities, using Simulink and Linux augmented with the BORPH operating system, provide a high level design environment. ...
Flexible Radio Testbeds are being designed using the Berkeley Emulation Engine (BEE2) platform. ...
The narrow-band system consists of a reconfigurable 2.4GHz radio modem. I/Q may be done in analog or digitally. ...
doi:10.1109/acssc.2007.4487585
fatcat:bjowfdxsffedhcjmt5t5wsugvi
Cognitive Radio Experiments using Reconfigurable BEE2
2006
2006 Fortieth Asilomar Conference on Signals, Systems and Computers
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However, most of these research results rely on a theoretical analysis or computer simulations. ...
The idea of cognitive radios has created a great interest in academic and industrial research. As a result, there are a large number of proposals for their physical and network layer functionalities. ...
However, for the detection of a signal of interest only the deterministic region of SCF needs to be computed. We developed a reconfigurable architecture for computation of any portion in NxN SCF. ...
doi:10.1109/acssc.2006.355125
fatcat:axqarb7xlvcmbdndll2msmofcy
Cyclostationary Feature Detector Experiments Using Reconfigurable BEE2
2007
2007 2nd IEEE International Symposium on New Frontiers in Dynamic Spectrum Access Networks
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We propose a new detector that overcomes this limitation, and characterize its performance through experiments. ...
In addition, the comparison with a conventional energy detector shows that feature detectors are more robust to adjacent channel interference. ...
Brodersen, "BEE2: A High-End Reconfigurable Computing System", in Proc. of IEEE Desing and Test of Computers, March 2005. [3] D. Cabric, A. Tkachenko, R. W. ...
doi:10.1109/dyspan.2007.36
fatcat:xyxkzkttqvd77e3w4xp7dju4ye
Guest Editors' Introduction: Advances in Configurable Computing
2005
IEEE Design & Test of Computers
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These include the authors who submitted articles, the reviewers, the editor in chief, and the editorial and production staff at the IEEE Computer Society. ...
The BEE2 project aims to create a universal reconfigurable computing system that can target a wide range of application domains, from high-performance digital signal processing (where FPGAs are already ...
It describes, from a practical perspective, the design of a second-generation, high-end reconfigurable computer consisting of commercial-offthe-shelf components, such as DRAM modules and standard network ...
doi:10.1109/mdt.2005.36
fatcat:tormrzxfcrfvpnl6ujpeueug64
Adventures with a Reconfigurable Research Platform
2007
2007 International Conference on Field Programmable Logic and Applications
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"I'm not interested in computing on multi-core
architectures, I want to compute on FPGAs."
Ivo Bolsens
Xilinx CTO
RAMP is not a "reconfigurable computing" project,
per se. ...
RAMP exposes FPGAs to many more grad students and faculty
research programs
Parallel Compilers and Languages
Operating systems and File Systems
Computer Architecture
Distributed Computing ...
doi:10.1109/fpl.2007.4380615
dblp:conf/fpl/Wawrzynek07
fatcat:6uiskuucjzfjlgipjcwcez5alm
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support
2006
2006 International Conference on Field Programmable Logic and Applications
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Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital ...
This paper presents BORPH, an operating system framework for FPGA-based reconfigurable computers with a goal to ease and accelerate development of high-level applications to run on these computers. ...
ACKNOWLEDGEMENTS This work cannot be completed without the endless effort by Pierre Droz and Andrew Schultz in developing many fundamental building blocks and infrastructures on BEE2 that BORPH is built ...
doi:10.1109/fpl.2006.311236
dblp:conf/fpl/SoB06
fatcat:6dwvxt7pmbc2xme2jvhnquiamu
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
2010
2010 International Conference on Field Programmable Logic and Applications
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We implemented application-specific DP algorithms for aligning data from ultra-high-throughput sequencers in a reconfigurable computing cluster. ...
We examine the advantages and practicality of our system by benchmarking real genomic data from a large sequencing project. ...
Reconfigurable Cluster Implementation Our multi-FPGA platform is implemented on a cluster of eight BEE2 systems, each connected via a TCP/IP switch to a central control server. ...
doi:10.1109/fpl.2010.121
dblp:conf/fpl/StevensCFMS10
fatcat:ryjzreisnncuvjuioi75f7buti
Virtualized Reconfigurable Hardware Resources in the SAVI Testbed
[chapter]
2014
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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on a testbed. ...
Reconfigurable hardware can allow acceleration of compute intensive tasks, provide line-rate packet processing capabilities, and in short, expand the range of experiments and applications that can be run ...
These reconfigurable hardware resources will enable a new range of applications and experiments that were previously unavailable in the SAVI testbed, and the networking testbed community at large. ...
doi:10.1007/978-3-319-13326-3_6
fatcat:xa2ticq62ncpndenzru65k5woa
Bringing up a chip on the cheap
2012
IEEE Design & Test of Computers
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The authors describe their creative solutions used to bring up Stanford Smart Memories (SSM), a 55-million transistor research chip. VNicola Nicolici, McMaster University ...
This material is based upon work partially supported under a Sequoia Capital Stanford Graduate Fellowship and The Sands Family Foundation. ...
Acknowledgment The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation subsidiary ...
doi:10.1109/mdt.2011.2179849
fatcat:4mewkquxvvbkbdvejgskutyujy
Current and Nascent SETI Instruments
[article]
2011
arXiv
pre-print
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Here we describe our ongoing efforts to develop high-performance and sensitive instrumentation for use in the search for extra-terrestrial intelligence (SETI). ...
, with reconfigurable, modular computing hardware in place of CPU compute nodes. ...
The reconfigurability of the PASP design makes the required size and computing power of the backend processing cluster highly elastic, scaling from a single server to a cluster of high-powered servers. ...
arXiv:1109.1136v1
fatcat:pqgqkuesg5dpzbc5qbudskcbwm
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
2008
ACM Transactions on Embedded Computing Systems
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This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers. ...
To develop hardware designs, a Simulink-based design flow that integrates with BORPH is employed. Performances of BORPH on two on-chip systems implemented on a BEE2 platform are compared. ...
ACKNOWLEDGMENTS The authors would like to thank Pierre Droz and Andrew Schultz for developing many fundamental BEE2 building blocks, and to thank Artem Tkachenko and Zhengya Zhang for testing various features ...
doi:10.1145/1331331.1331338
fatcat:5kvg526ccjdyjpcylgrxsgcsry
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
2006
Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06
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This paper explores the design and implementation of BORPH, an operating system designed for FPGA-based reconfigurable computers. ...
To develop hardware designs, a Simulink-based design flow that integrates with BORPH is employed. Performances of BORPH on two on-chip systems implemented on a BEE2 platform are compared. ...
ACKNOWLEDGMENTS The authors would like to thank Pierre Droz and Andrew Schultz for developing many fundamental BEE2 building blocks, and to thank Artem Tkachenko and Zhengya Zhang for testing various features ...
doi:10.1145/1176254.1176316
dblp:conf/codes/SoTB06
fatcat:777icmx5mref3c4epxc6m6t53u
RAMP Blue: A Message-Passing Manycore System in FPGAs
2007
2007 International Conference on Field Programmable Logic and Applications
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The system consists of 768-1008 MicroBlaze cores in 64-84 Virtex-II Pro 70 FPGAs on 16-21 BEE2 boards, surpassing the milestone of 1000 cores in a standard 42U rack. ...
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. ...
We would also like to thank Chen Chang, Henry Chen, and Dan Burke for all their work in creating the BEE2. This work was funded in part by the National Science ...
doi:10.1109/fpl.2007.4380625
dblp:conf/fpl/KrasnovSWGD07
fatcat:2xuhslh3ajb5fmdoktmh4l2yja
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