Filters








1,495 Hits in 6.2 sec

Average-case optimized transistor-level technology mapping of extended burst-mode circuits

K.W. James, K.Y. Yun
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems  
We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers.  ...  The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal performance for the average or common case. *  ...  Overview This section describes extended burst-mode circuits, and an overview of the average-case optimized technology mapping, using a simple example.  ... 
doi:10.1109/async.1998.666495 dblp:conf/async/JamesY98 fatcat:d3ktyw5lb5bb5aut4fnqfvdvj4

Transistor analogs of emergent iono‐neuronal dynamics

Guy Rachmuth, Chi‐Sang Poon
2008 HFSP Journal  
Neuromorphic analog metal-oxide-silicon "MOS... transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation.  ...  As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an  ...  The aVLSI chips were fabricated with the support of the MOSIS Education Program. GR was a recipient of the U.S.  ... 
doi:10.2976/1.2905393 pmid:19404469 pmcid:PMC2645565 fatcat:ihcehnbyy5ffjdlhdf2sq5qtxq

Power Optimized Transceivers for Future Switched Networks

Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore, Andrew W. Moore
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We propose a burst mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b but, even without power gating and VCO power optimization  ...  To understand and decompose transceiver power-consumption, we create a toolkit incorporating a library of transceiver circuits in 45 nm CMOS and MCML (MOS Current Mode Logic) and characterise power consumption  ...  The circuit is designed for burst mode operation. III.  ... 
doi:10.1109/tvlsi.2013.2283300 fatcat:eo32s3rpdfek5ae3n3u2amlxci

CAD directions for high performance asynchronous circuits

Ken Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
It supports the specification, synthesis, and verification of high-performance asynchronous circuits, such as pulse-mode circuits, that can be derived from an initial speed-independent specification.  ...  Silicon results show significant advantages -in particular, performance of 2.5-4.5 instructions per nS -with manageable risks using this design technology.  ...  Alex Kondratyev, Luciano Lavagno, Alexander Taubin, and Alex Yakovlev contributed to the developing of the relative timing synthesis.  ... 
doi:10.1145/309847.309893 dblp:conf/dac/StevensRBCGKR99 fatcat:gu5gqkwcpzc7xlitswviw63xza

Static NBTI Reduction Using Internal Node Control

David R. Bild, Robert P. Dick, Gregory E. Bok
2012 ACM Transactions on Design Automation of Electronic Systems  
Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units, because these units can be subjected to static NBTI stress for extended periods of time  ...  This near-optimality is confirmed by comparing results for small benchmarks against optimal solutions from a mixed integer linear programming formulation of our problem.  ...  ., changing the technology mapping solution. As a result, this apparently straightforward change in optimization constraints and objectives would couple multiple steps of the design process.  ... 
doi:10.1145/2348839.2348849 fatcat:l6dax3jcsjg53g5sc53bskkwoe

Parameter Estimation of a Spiking Silicon Neuron

Alexander Russell, Kevin Mazurek, Stefan Mihalas, Ernst Niebur, Ralph Etienne-Cummings
2012 IEEE Transactions on Biomedical Circuits and Systems  
Spiking neuron models are used in a multitude of tasks ranging from understanding neural behavior at its most basic level to neuroprosthetics.  ...  We conclude that the distance based method is better suited for parameter configuration of silicon neurons due to its superior optimization speed.  ...  Acknowledgments This work was supported by the Office of Naval Research under MURI Grant N000141010278 and NIH-NEI 5R01EY016281-02.  ... 
doi:10.1109/tbcas.2011.2182650 pmid:23852978 pmcid:PMC3712290 fatcat:nm42ys6ijnb45efckgowbu73u4

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi
2008 SIGARCH Computer Architecture News  
We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.  ...  technology node.  ...  Acknowledgments We would like to thank Arun Lokanathan of Micron Technology for helping improve our understanding of commodity DRAM, and Wolfgang Mueller of Qimonda for providing data associated with his  ... 
doi:10.1145/1394608.1382127 fatcat:5sohd4d3gfhz3jqao4lfyrzxsa

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi
2008 2008 International Symposium on Computer Architecture  
We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.  ...  technology node.  ...  Acknowledgments We would like to thank Arun Lokanathan of Micron Technology for helping improve our understanding of commodity DRAM, and Wolfgang Mueller of Qimonda for providing data associated with his  ... 
doi:10.1109/isca.2008.16 dblp:conf/isca/ThoziyoorAMBJ08 fatcat:wo7q5odufbfwrpp5f3u3nhqguq

Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes

Prabhakar Kudva, Ganesh Gopalakrishnan, Hans Jacobson, Steven M. Nowick
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
This paper addresses the problem of realizing hazard-free singleoutput Boolean functions through a network of customized complex CMOS gates tailored to a given asynchronous controller specification.  ...  A customized CMOS gate network can either be a single CMOS gate or a multilevel network of CMOS gates.  ...  This problem is encountered during the synthesis of burst-mode circuits [8, 15] and is a general problem in asynchronous synthesis.  ... 
doi:10.1145/240518.240534 dblp:conf/dac/KudvaGJN96 fatcat:jt7tgfvwubcy5eqq6g6zp77rx4

Platune: a tuning framework for system-on-a-chip platforms

T. Givargis, F. Vahid
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Platune is used to simulate an embedded application that is mapped onto the SOC platform and output performance and power metrics for any configuration of the SOC platform.  ...  The versatility, in terms of accuracy and speed of exploration, of Platune is demonstrated experimentally using three large benchmark examples.  ...  ., first read/write from a page in burst mode) or a subsequent read/write operation from a page in burst mode.  ... 
doi:10.1109/tcad.2002.804107 fatcat:offtu63dazg4xdaqasdtda5gku

Digital implementation of a wavelet-based event detector for cardiac pacemakers

J.N. Rodrigues, T. Olsson, L. Sornmo, V. Owall
2005 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
Due to a 0.13-m CMOS technology and the low clock frequency of 1 kHz, leakage power becomes the dominating power source.  ...  By introducing sleep transistors in the power-supply rails, leakage power of the hardware being shut off is reduced by 97%.  ...  Gate-level power estimation predicts 67% power savings if operating in normal mode; no performance degradation is measurable for such cases.  ... 
doi:10.1109/tcsi.2005.857925 fatcat:lvc32y7c5nhsldcyxkbr6wglqe

Burst-mode asynchronous controller implementation on FPG using relative timing

Jotham Vaddaboina Manoranjan, Kenneth S. Stevens
2014 2014 IX Southern Conference on Programmable Logic (SPL)  
The method presented in this paper can be used to implement a wide variety of burst-mode controllers, across various FPGAs.  ...  A new methodology for the design of glitch free burst-mode asynchronous controllers on FPGAs is presented. The approach is based on relative timing, which enables timing driven asynchronous design.  ...  Such a solution should work well for burst-mode controllers which typically map to a very small number of LUTs, and in most case can implemented within a single CLB.  ... 
doi:10.1109/spl.2014.7002213 fatcat:iuf2k67n4zhxvabvxnlpydc7ke

Energy-efficiency improvements for optical access

Peter Vetter, Dusan Suvakovic, Hungkei Chow, Prasanth Anthapadmanabhan, Konstantinos Kanonakis, Ka-lun Lee, Fabienne Saliou, Xin Yin, Bart Lannoo
2014 IEEE Communications Magazine  
These approaches include cyclic sleep mode, energy-efficient bit interleaving protocol, power reduction at component level, or frequency band selection.  ...  Depending on the target optical access technology, one or a combination of different approaches can be applied.  ...  Kanonakis is a member of the IEEE, the IEEE Communications Society and the Technical Chamber of Greece. Ka-Lun  ... 
doi:10.1109/mcom.2014.6807958 fatcat:mpw5uraajba73alu2ago2kbycm

Optimization of NULL convention self-timed circuits

S.C. Smith, R.F. DeMara, J.S. Yuan, D Ferguson, D. Lamb
2004 Integration  
On the other hand, bounded-delay models such as Huffman circuits [18], burst-mode circuits [19] , and micropipelines [20] assume that delays in both gates and wires are bounded.  ...  TCR optimizations are formalized for NCL and then assessed by comparing levels of gate delays, gate counts, transistor counts, and power utilization of the resulting designs.  ...  The results can also be extended to a gate-level pipelining strategy for circuits composed of stateholding elements to maximize throughput of combinational circuits produced by TCR methods as ARTICLE  ... 
doi:10.1016/j.vlsi.2003.12.004 fatcat:vpiscavpr5dozeaq3extbo66wa

Designing optimal energy profiles for network hardware

Raffaele Bolla, Roberto Bruschi, Franco Davoli
2012 2012 IEEE Global Communications Conference (GLOBECOM)  
This approach will allow us to gain insight in the behavior of the optimal solutions that achieve different desired tradeoffs.  ...  In particular when designing network hardware, one should address the problem of optimizing parameter values (most often chosen in a discrete set) to trade-off energy efficiency and network performance  ...  Without losing of generality, this section introduces the main benefits and drawbacks of power management for the CMOS technologies. Such considerations can be easily extended to other technologies.  ... 
doi:10.1109/glocom.2012.6503585 dblp:conf/globecom/BollaBD12 fatcat:loljmybe5zhsrdgvp2ydb5r3ru
« Previous Showing results 1 — 15 out of 1,495 results