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Factors Influencing Edge Smoothing Effects in Optical Packet Switched Networks
2006
2006 International Conference on Photonics in Switching
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It smoothes external traffic at optical edge ingress switches, so that the traffic pattern flowing into the core is more regular. ...
Through simulation, the effect of this edge smoothing scheme in reducing optical packet loss in the core is quantified, and compared to the performance when using containerization without any traffic smoothing ...
Figure 4 : 4 Optical packet loss rate versus core switch FDL buffer depth for various numbers of flows.
Table 1 : 1 Loss rate of core switch under different scenarios. ...
doi:10.1109/ps.2006.4350130
fatcat:6wii4526dbdfzjoehc3nr5lzzq
Design of an Inductive Adder for the FCC injection kicker pulse generator
2017
Journal of Physics, Conference Series
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It outlines the results from simulations and measurements on different magnetic core materials as well as on SC switches. ...
An inductive adder (IA) based on semiconductor (SC) switches is a promising technology for kicker systems. ...
IGBTs are available up to several hundred Amps and several kV, but do not have the required fast switching times. ...
doi:10.1088/1742-6596/874/1/012096
fatcat:5csyv3exjfanfptg2n4wx3jc4e
Traffic Grooming and QoS Management over OLS Networks
2014
OALib
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The proposed scheme tries to increase the usage of the available resources in terms of Optical Delay Line (ODL) and wavelength conversion. ...
In this paper, we proposed a real-t ime traffic groo ming scheme through the use of an upgraded OLS core node architecture that can efficiently integrate several input traffics on the unique output port ...
Knowing that, an OLS 21 network can be assumed as a set of edges and cores nodes interconnected with a set of available 22 wavelengths where the edge and core nodes will cooperate for establishing a suitable ...
doi:10.4236/oalib.preprints.1200050
fatcat:organ3cbrrbcjaorqvuo5yd7rq
Scale-Out Networking in the Data Center
2010
IEEE Micro
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A 1,024-port 10 Gigabit Ethernet pod switch with 10.24 terabits per second (Tbps) of uplink capacity to a core switch array. ...
Thus, we reduce the previously required 5,120 individual switches to 64 pod switches and one core switch array, and the 131,072 required cables to 64. ...
doi:10.1109/mm.2010.72
fatcat:q7o2qthicjd6bah3ec364ugsmq
Page 32 of IBM Journal of Research and Development Vol. 4, Issue 4
[page]
1960
IBM Journal of Research and Development
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Although the matrix switch provides larger, faster drive pulses than were avail- able previously, it requires a comparatively large number of drivers as inputs. Marcus? ...
The size of the cores, the core material, the number of turns, et cetera, must be chosen according to the methods of pulse trans- former design to fit the requirements of the matrix switch logic. ...
Oversubscription Bounded Multicast Scheduling in Fat-Tree Data Center Networks
2013
2013 IEEE 27th International Symposium on Parallel and Distributed Processing
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high degree of link parallelism. ...
Multicast benefits numerous data center applications that require group communication by eliminating sending unnecessary duplicated packets in the network, thus significantly reduces network traffic and ...
We refer to the set of core switches connected by (O, ω)available uplinks from edge switch i as (O, ω)-available core switches. ...
doi:10.1109/ipdps.2013.30
dblp:conf/ipps/GuoDY13
fatcat:2nznkccbxbgcdg6myv6fffcvzu
Automated Design of Two-Layer Fat-Tree Networks
[article]
2013
arXiv
pre-print
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The algorithm is useful as a part of a bigger design procedure that selects optimal hardware of cluster supercomputer as a whole. ...
The two levels may each use a different type of switches from design database to achieve an optimal network structure. Links between layers can run in bundles to simplify cabling. ...
The latter scenario can, in very rare cases, lead to a lower number of required core switches. ...
arXiv:1301.6179v1
fatcat:kij2fhs2dnc4dke2cldakx7iiu
An analysis of time-synchronized optical burst switching
2006
2006 Workshop on High Performance Switching and Routing
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While more FDLs available in an OBS node means better blocking probability, additional FDL in a core node requires additional physical requirements in core switching fabric. ...
This requires fewer 2x2 switching devices in the core switching fabric, which implies a lower cost of implementation. ...
doi:10.1109/hpsr.2006.1709736
fatcat:5jjnnzqhd5ddde4hlvalijb6tu
Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture
[chapter]
2017
Lecture Notes in Computer Science
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In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. ...
In this paper, we first present a concept of optically connected memory modules, delivering enough bandwidth to allow for cache reduction and memory externalization. ...
The rationale of the concept can be described through a few examples: in situations where the memory storage available in a single module is actively solicited by numerous cores, the SiP switch can be ...
doi:10.1007/978-3-319-67630-2_7
fatcat:q4vuhpdy7fgnhmwvdtvtgzbl7y
On-Line Multicast Scheduling with Bounded Congestion in Fat-Tree Data Center Networks
2014
IEEE Journal on Selected Areas in Communications
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Hence, in this paper we study multicast flow scheduling in fat-tree DCNs, where multicast flow requests arrive one by one without a priori knowledge of future traffic. ...
Multicast benefits numerous data center applications that require group communication by eliminating sending unnecessary duplicated packets in the network, thus significantly reduces network traffic and ...
, the set of (C, ω)-available core switches T . ...
doi:10.1109/jsac.2014.140110
fatcat:chjnlptjfbgrjd2q7exeufmhra
A scalable, commodity data center network architecture
2008
Proceedings of the ACM SIGCOMM 2008 conference on Data communication - SIGCOMM '08
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The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. ...
Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring ...
Acknowledgments We wish to thank George Varghese as well as the anonymous referees for their valuable feedback on earlier drafts of this paper. ...
doi:10.1145/1402958.1402967
dblp:conf/sigcomm/Al-FaresLV08
fatcat:372nu6umpne4naamikz5zaoxn4
A scalable, commodity data center network architecture
2008
Computer communication review
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The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. ...
Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring ...
Acknowledgments We wish to thank George Varghese as well as the anonymous referees for their valuable feedback on earlier drafts of this paper. ...
doi:10.1145/1402946.1402967
fatcat:m34tpdvkebaixb5svbpmi7o4lu
FOSquare: A Novel Optical HPC Interconnect Network Architecture Based on Fast Optical Switches with Distributed Optical Flow Control
2021
Photonics
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The numerical results show that the FOSquare can reduce >10% latency with respect to Leaf-Spine under the scenario of 16 available cores. ...
Interconnecting networks adopting Fast Optical Switches (FOS) can achieve high bandwidth, low latency, and low power consumption. ...
Three scenarios with 16, 32 and 64 available cores are taken into consideration. The index array of the available cores is obtained in advance. ...
doi:10.3390/photonics8010011
fatcat:qsnmqzucuvca5kjwkupij2mpdq
ATLAS TDAQ DataFlow network architecture analysis and upgrade proposal
2006
IEEE Transactions on Nuclear Science
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After examining the functional and performance requirements of the network, several design alternatives (with respect to traffic repartition on core devices and available concentration technologies) are ...
We introduce the use of 10 Gigabit Ethernet as a flexible and simple technology for concentrating traffic. ...
Distributing the network core over two devices, each handling a mixture of level two and event building traffic, improves the fault tolerance of the system, while reducing the size of the required switches ...
doi:10.1109/tns.2006.873302
fatcat:676s67mm2fcijh4n57wm6c7uzi
ATLAS TDAQ dataflow network architecture analysis and upgrade proposal
2005
14th IEEE-NPSS Real Time Conference, 2005.
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After examining the functional and performance requirements of the network, several design alternatives (with respect to traffic repartition on core devices and available concentration technologies) are ...
We introduce the use of 10 Gigabit Ethernet as a flexible and simple technology for concentrating traffic. ...
Distributing the network core over two devices, each handling a mixture of level two and event building traffic, improves the fault tolerance of the system, while reducing the size of the required switches ...
doi:10.1109/rtc.2005.1547531
fatcat:4sl2gvrpzzefbpheqxyyhiscsa
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