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Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis

Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz Czajkowski, Stephen Brown, Jason Anderson
2014 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing  
The hybrid system comprises an embedded processor and custom accelerators that realize user-designated compute-intensive parts of the program with improved throughput and energy efficiency.  ...  Since its first release in 2011, LegUp has been downloaded over 1000 times by groups around the world, providing a powerful platform for new research in high-level synthesis algorithms and embedded systems  ...  COMPARISON AGAINST LEGUP 3.0 We compared the quality of results provided by the current LegUp tool, with that provided by the 3.0 release (early 2013).  ... 
doi:10.1109/euc.2014.26 dblp:conf/euc/FortCCCLHCHSCBA14 fatcat:gm6y5hryjjghjdfws74y7jzody

From software to accelerators with LegUp high-level synthesis

Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz Czajkowski, Stephen Brown, Jason Anderson
2013 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)  
With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA.  ...  LegUp is an open-source highlevel synthesis framework that simplifies the hardware accelerator design process [8] .  ...  The financial support of the Natural Sciences and Engineering Research Council of Canada (NSERC) and Altera Corporation is gratefully acknowledged.  ... 
doi:10.1109/cases.2013.6662524 dblp:conf/cases/CanisCFLHCGQACBA13 fatcat:mkl646vbefa43irr2i725vmh6u


Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H. Anderson, Stephen Brown, Tomasz Czajkowski
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool.  ...  In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design.  ...  CONCLUSIONS In this paper, we introduced LegUp -a new high-level synthesis tool that compiles a standard C program to a hybrid processor/accelerator architecture.  ... 
doi:10.1145/1950413.1950423 dblp:conf/fpga/CanisCAZKABC11 fatcat:kcbhrxlyzbhsle3ojzt53wlgwa

Introduction to the special issue on application-specific processors

Philip Brisk, Tulika Mitra
2013 ACM Transactions on Embedded Computing Systems  
Application-specific architectures are often derived from a high-level specification of an application through a hardware/software co-design process, which can be highly automated; such a process would  ...  Moreover, code compilation targeting application-specific processors is often intertwined with the co-design process.  ...  "LegUp: An Open-Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems" by Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz Czajkowski, Stephen D.  ... 
doi:10.1145/2514641.2514642 fatcat:yt4boxsh2jghzppzoardzpv4oa

Bitwidth-optimized hardware accelerators with software fallback

Ana Klimovic, Jason H. Anderson
2013 2013 International Conference on Field-Programmable Technology (FPT)  
We propose the high-level synthesis of an FPGAbased hybrid computing system, where the implementations of compute-intensive functions are available in both software, and as hardware accelerators.  ...  The selected widths are passed to a high-level synthesis tool which generates the accelerator for a given function.  ...  ACKNOWLEDGMENT The authors would like to thank Marcel Gort for his work and much-appreciated guidance on dynamic range analysis in LegUp which served as the starting point of this paper.  ... 
doi:10.1109/fpt.2013.6718343 dblp:conf/fpt/KlimovicA13 fatcat:4pos7da7uvafxl72uiqrsnaf4a

From software threads to parallel hardware in high-level synthesis for FPGAs

Jongsok Choi, Stephen Brown, Jason Anderson
2013 2013 International Conference on Field-Programmable Technology (FPT)  
We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP.  ...  Both data parallelism and task-level parallelism are supported, as is the combined use of both Pthreads and OpenMP.  ...  The baseline configuration is the default LegUp hybrid processor/accelerator system, with no accelerators that operate in parallel -the processor and accelerators operate sequentially and the processor  ... 
doi:10.1109/fpt.2013.6718365 dblp:conf/fpt/ChoiBA13 fatcat:pcv44xt7l5dr3oafllvqxs6qcq

Towards Test-Driven Development for FPGA-based Modules Across Abstraction Levels

Julian Caba, Fernando Rincon, Jesus Barba, Jose A. De La Torre, Julio Dondo, Juan C. Lopez
2021 IEEE Access  
High-Level Synthesis (HLS) tools help engineers to deal with the complexity of building heterogeneous embedded systems that make it use of reconfigurable technology.  ...  INDEX TERMS Design for testability, on-board verification, high-level synthesis, FPGA, unit testing framework, test-driven design. JUAN C.  ...  PROCESSOR/ACCELERATOR LEVEL: SOFTWARE SIMULATION Along with the model of the component (i.e. the functionality to be accelerated and deployed in the FPGA), a functional verification must be performed and  ... 
doi:10.1109/access.2021.3059941 fatcat:4g5hpe5rsnfufnco5f2g2wtt2m

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jurgen Becker, Koen Bertels
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
A good interconnect design plays a key role in improving the performance of such systems.  ...  The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories.  ...  LegUp [6] is an open source high-level synthesis tool for FPGA-based processor/accelerators systems.  ... 
doi:10.7873/date.2013.178 dblp:conf/date/Pham-QuocHWABB13 fatcat:cbgeh6sa3jh4vob54hcn577ifm

Harnessing Adaptivity Analysis for the Automatic Design of Efficient Embedded and HPC Systems

Silvia Lovergine, Fabrizio Ferrandi
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
Such a scheduling technique, called dynamic AC-scheduling, provides support for the High-Level Synthesis (HLS) of adaptive hardware cores.  ...  Embedded Systems (ESs) and High-Performance Computing (HPC) systems belong to two distinct areas of the Information Technology (IT).  ...  High-Level Synthesis The term High-Level Synthesis (HLS) indicates a design process which, given an abstract (unclocked, or partially clocked) behavioral specification of a digital system (e.g., C, C++  ... 
doi:10.1109/ipdpsw.2013.230 dblp:conf/ipps/LovergineF13 fatcat:vpdgybp2gnbmve6wzgscv6hqoa

Rapid digital architecture design of orthogonal matching pursuit

Benjamin Knoop, Jochen Rust, Sebastian Schmale, Dagmar Peters-Drolshagen, Steffen Paul
2016 2016 24th European Signal Processing Conference (EUSIPCO)  
The proposed methodology is founded on the enormous capabilities of High-Level Synthesis (HLS), which basically is a synthesis step to compile concurrently operating VLSI architectures from sequentially  ...  to a higher level of abstraction-the algorithmic level.  ...  LegUp can either compile a digital hardware design or a hybrid processor-accelerator system. The input language is C.  ... 
doi:10.1109/eusipco.2016.7760570 dblp:conf/eusipco/KnoopRSPP16 fatcat:bo3c4fo6njeo3hjjsnwo72jbwe

Quality-driven model-based design of multi-processor accelerators:an application to LDPC decoders [article]

Jan, Y (Yahya), Pineda De Gyvez, J (José), Jozwiak, L (Lech)
High-Level-Synthesis Tools Integration Since the micro-architecture synthesis for hardware processors is one of the main part of the proposed multi-processor accelerator design methodology, HLS tools could  ...  synthesis, as well as, of memory partitioning, data distribution and related data mapping were incorporated into the multi-processor accelerator design method and related automated architecture exploration  ...  Results of his PhD research project include: a method for multi-processor hardware accelerator design and related prototype design automation tool, as well as, his PhD thesis and several journal and conference  ... 
doi:10.6100/ir732195 fatcat:s35g3keguzhmlplmqumalno64u

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George
high-level functional specifications.  ...  However, most synthesis tools require users to have hardware design knowledge to produce high-quality results.  ...  ROCCC and LegUp are open-source tools that are being developed in the academia; among them LegUp can generate standalone hardware implementations as well as processor-accelerator architectures targeting  ... 
doi:10.5075/epfl-thesis-7004 fatcat:mkc7f3zarvgz7ndkc4gxqqwxfy

Compiler Analysis for Hardware/Software Co-design and Optimization

Georgios Zacharopoulos
2020 unpublished
, the employed bus protocol, the interconnect strategy and the number of considered processors, accelerators and memories.  ...  Their design however ultimately needs to be manually implemented and hence the work neglects High Level Synthesis aspects.  ...  manual decisions of a designer.  ... 
doi:10.13140/rg.2.2.23474.96966 fatcat:3ponlmvsure6jevkkdexo6ut3e


The many system-level architectural aspects to consider make it hard to explore the design space and arrive to optimal solutions.  ...  This improves their reusability across SoC platforms, while ensuring correctness when the accelerators are integrated with the various components of the SoC.  ...  Part II Design-Space Exploration System-Level Design (SLD) methodologies [25, 194] and High-Level Synthesis (HLS) [51, 139, 148] , have, however, come to the rescue by raising the level of abstraction  ... 
doi:10.7916/btpm-jm27 fatcat:os4yxgcgkranjd5y7gz2xccoti

OASIcs, Volume 100, PARMA-DITAM 2022, Complete Volume [article]

Francesca Palumbo, João Bispo, Stefano Cherubin
Legup: An open-source high-level synthesis tool for fpga-based processor/accelerator systems. ACM Transactions on Embedded Computing Systems (TECS), 13(2):1-27, 2013. 4 Davor Capalija.  ...  A complete host processor-accelerator environment, with proper Operating System support is under development.  ...  A profiling system was also introduced in order to keep track of the number of heap allocations and deallocations executed during the simulation, together with the time spent in doing such operations.  ... 
doi:10.4230/oasics.parma-ditam.2022 fatcat:jqaiw7ckvjbjbaklqq7izl73mu