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Automating verification by functional abstraction at the system level
[chapter]
1994
Lecture Notes in Computer Science
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The contribution of this paper is therefore a new design style based on handshake circuits and a highly automated approach to verification at the system level ba~ed on functional abstraction. * This work ...
The verification of digital circuits at higher levels of abstraction still suffers from complex and unstructured proofs. ...
at the system level. ...
doi:10.1007/3-540-58450-1_56
fatcat:eqssb76kebd6fnp7okdnf52fcu
Maintaining consistency between SystemC and RTL system designs
2006
Proceedings - Design Automation Conference
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This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level. ...
We describe how system design consistency can be maintained across multiple levels of design abstraction using a modular verification IP strategy. ...
to be automated across the entire system-level modeling and verification flow. ...
doi:10.1109/dac.2006.229178
fatcat:jng6yx5utfgtnnqie6jm2yho7e
Maintaining consistency between systemC and RTL system designs
2006
Proceedings of the 43rd annual conference on Design automation - DAC '06
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This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level. ...
We describe how system design consistency can be maintained across multiple levels of design abstraction using a modular verification IP strategy. ...
to be automated across the entire system-level modeling and verification flow. ...
doi:10.1145/1146909.1146936
dblp:conf/dac/BruceHNBRL06
fatcat:uuys6vtjyzegtlvgdjr3kdz43e
PhD Abstracts
2020
Journal of functional programming
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As a service to the community, twice per year the Journal of Functional Programming publishes the abstracts from PhD dissertations completed during the previous year. ...
Many students complete PhDs in functional programming each year. ...
Dissertation Abstract: Call-by-need semantics formalize the wisdom that work should be done at most once. ...
doi:10.1017/s0956796819000200
fatcat:rsyetan23fgzzhrg7vlk3h2frm
The Challenge of Hardware-Software Co-verification
[chapter]
2008
Lecture Notes in Computer Science
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To what extent can the process be automated? We address these issues, using as a running example our recent and on-going work on refinement-based pipelined machine verification. ...
Building verified computing systems such as a verified compiler or operating system will require both software and hardware verification. ...
Introduction The ultimate goal of the formal verification community is to mechanically verify computing systems from the subatomic level up to high-level specifications. ...
doi:10.1007/978-3-540-69149-5_47
fatcat:e732c2plifcq5ksaroq3aymgwe
Property-based Code Slicing for Efficient Verification of OSEK/VDX Operating Systems
2012
Electronic Proceedings in Theoretical Computer Science
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2013 pre-print arXiv:1301.0042v1 fatcat:qidqd263efcsto5f6tzkxnoqt4
The technique is automated and applied to an OSEK/VDX-based automotive operating system, Trampoline. ...
On the other hand, model checking is a powerful technique that supports comprehensiveness, and is thus suitable for the verification of safety-critical systems. ...
Property-based abstraction: The operating system kernel is abstracted by extracting only the code relevant to a given property. ...
doi:10.4204/eptcs.105.6
fatcat:znnzq33siveazkiqueixhy2qde
Verification strategy for integration 3G baseband SoC
2003
Proceedings of the 40th conference on Design automation - DAC '03
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the abstraction level. ...
Adaptive verification scenarios are discussed across the abstraction levels and the SoC hierarchy, from stand-alone IP verification, through sub platforms and to the SoC level. ...
Therefore, the SoC architecture model needs to cope with such complexity and be able to capture system components at a high level of abstraction. ...
doi:10.1145/775833.775835
fatcat:drpwue65lrbbjbymod7rqpq4si
Verification strategy for integration 3G baseband SoC
2003
Proceedings of the 40th conference on Design automation - DAC '03
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the abstraction level. ...
Adaptive verification scenarios are discussed across the abstraction levels and the SoC hierarchy, from stand-alone IP verification, through sub platforms and to the SoC level. ...
Therefore, the SoC architecture model needs to cope with such complexity and be able to capture system components at a high level of abstraction. ...
doi:10.1145/775832.775835
dblp:conf/dac/MathysC03
fatcat:wviabrbrrrai7n6l7ymxmpar24
SFB/TR 14 AVACS – Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS – Automatische Verifikation und Analyse komplexer Systeme)
2007
it - Information Technology
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The Transregional Collaborative Research Center AVACS integrates the three sites Freiburg, Oldenburg, and Saarbrücken, and addresses the challenge of pushing the borderline for automatic verification and ...
AVACS is organized in ten subprojects, each teaming researchers from all sites, and is funded by the German Science Foundation since January 1, 2004. ...
At the specification level they describe the required functionality and real-time behavior of the system as seen by the environment of the system. ...
doi:10.1524/itit.2007.49.2.118
fatcat:2mb2uwdoazcirmt7ghfq3p7aua
A Framework for Model and Verification of Safety-Critical Operating System Based on ARINC653
2021
Electronics
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Experience shows that the verification system we developed can be achieved the functional correctness of a complete OS with a low implement burden, and that can simplify the difficulty of automated verification ...
However, design a high assurance safety-critical system by formal methods is challenging due to the complexity of operating systems. ...
It will provide a new idea for formal verification at the operating system level. ...
doi:10.3390/electronics10161934
fatcat:i7gom7oesnfuphgkw46osf6c3u
Nuts and bolts of core and SoC verification
2001
Proceedings of the 38th conference on Design automation - DAC '01
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Digital design at Motorola is performed at design centers throughout the world, on projects with different design objectives, executed on different time scales, by different sized teams with different ...
This paper attempts to categorize these diverse efforts and identify common threads: what works, what the challenges are, and where we need to go. ...
and reusing them at different levels of hierarchy • the extensive use of constrained random stimulus • automation to manage/navigate data • appropriate use of abstraction The underlying problem that verification ...
doi:10.1145/378239.378475
dblp:conf/dac/Albin01
fatcat:72e7qzcznjdpzp6ehxqbtzlk3e
Reasoning and Verification: State of the Art and Current Trends
2014
IEEE Intelligent Systems
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In this article, the authors give an overview of toolbased verification of hardware and software systems and discuss the relation between verification and logical reasoning. reiner Hähnle is a professor ...
Acknowledgment We thank the anonymous reviewers for their careful reading of this article and numerous valuable suggestions for improvement. ...
The approach's main difference from functional verification is that the refinement spans more levels and starts at the most abstract level. ...
doi:10.1109/mis.2014.3
fatcat:dm3azbzibvhx7n7sgkrbdmufsa
Tools for model-based security engineering
2006
Proceeding of the 28th international conference on Software engineering - ICSE '06
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We focus on a verification routine that automatically verifies crypto-based software for security requirements by using automated theorem provers. ...
A framework supports implementing verification routines, based on XMI output of the diagrams from UML CASE tools, and on control flow generated from the C code. ...
At the hand of the verification of security properties, we use automated theorem provers for first-order logic for automated verification of state machines generated from code in a combination with using ...
doi:10.1145/1134285.1134423
dblp:conf/icse/JurjensF06
fatcat:amyu7yvrjvg4bgin5atfaidcce
Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]
2015
Proceedings of the IEEE
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The ability to independently specify, design, and assemble electronic systems at various abstraction levels has enabled tremendous growth in the semiconductor industry. ...
These issues highlighted the need to raise the level of abstraction for hardware specification above registerYtransfer level (RTL) design. ...
doi:10.1109/jproc.2015.2487798
fatcat:4awt5m25mjfpdkpxzvyznx233m
A Unique Test Bench for Various System-on-a-Chip
2017
International Journal of Electrical and Computer Engineering (IJECE)
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By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today's technology. ...
The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.</p> ...
In order to construct the last type of virtual sequences reusable at chip-level, it is better to plan ahead to abstract the data from the protocol. ...
doi:10.11591/ijece.v7i6.pp3318-3322
fatcat:wl2ue663azgcbkqpfisdxpxqsy
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