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Automatically partitioning packet processing applications for pipelined architectures

Jinquan Dai, Bo Huang, Long Li, Luddy Harrison
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/jpubwsjaozha5itdes6pzyz2fm" style="color: black;">Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation - PLDI &#39;05</a> </i> &nbsp;
Our proposed method automatically partitions a sequential packet processing application into coordinated pipelined parallel subtasks which can be naturally mapped to contemporary highperformance network  ...  For a 9-stage pipeline, our auto-partitioning C compiler obtained more than 4X speedup for the IPv4 forwarding PPS and the IP forwarding PPS (for both the IPv4 traffic and IPv6 traffic).  ...  Acknowledgements The authors would like to thank Wen-Hann Wang for providing insightful suggestions on revising the paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1065010.1065039">doi:10.1145/1065010.1065039</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/pldi/DaiHLH05.html">dblp:conf/pldi/DaiHLH05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mf4xkiwe65fctbpstlldrdhy54">fatcat:mf4xkiwe65fctbpstlldrdhy54</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190217233547/https://static.aminer.org/pdf/20170130/pdfs/pldi/slmnbwev4tajo2y7viya5cdknkwst1rf.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/31/2a/312ae7a6784ada2f0c8b7021b678a3f028eb0636.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1065010.1065039"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors [chapter]

Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
<span title="">2004</span> <i title="Elsevier"> Network Processor Design </i> &nbsp;
Network processors exploit task and packet level parallelism to achieve high throughput. To date, this has resulted in a huge diversity of architectures for similar applications.  ...  Architecture Application Mapping Evaluation Service curves Task graph and arrival curves Binding of tasks and communication Worst-case packet delay Resource utilization Memory requirements Architecture  ...  In addition, we also recognize that given an application task graph, automatic refinement of the task graph needs to be performed for mapping applications to architectures in general.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/b978-012198157-0/50009-x">doi:10.1016/b978-012198157-0/50009-x</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7dkmymrfbfgdhoahewbylztmhq">fatcat:7dkmymrfbfgdhoahewbylztmhq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100730114550/http://www.eecs.berkeley.edu/IPRO/VIF/Papers/GKSK_np2_book_1col_single.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e1/8a/e18ada804acd6f56a9c4aaccc260e82b6be47d28.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/b978-012198157-0/50009-x"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> elsevier.com </button> </a>

Practice of parallelizing network applications on multi-core architectures

Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang
<span title="">2009</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3sq4a52jknfqpfyjfszyrlkedm" style="color: black;">Proceedings of the 23rd international conference on Conference on Supercomputing - ICS &#39;09</a> </i> &nbsp;
as the first design principles; (2) a delicate partitioning scheme is required to map pipelined structures onto specific multi-core architecture; (3) an automatic parallelization approach can work if  ...  Our multi-core based network processing platform can deliver not only 6Gbps processing speed for large packet sizes but also more challenging 2Gbps speed for smaller packets.  ...  Acknowledgements We would like to thank the anonymous reviewers for their valuable comments. This work was supported by the National Natural Science References  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1542275.1542307">doi:10.1145/1542275.1542307</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ics/WangCHT09.html">dblp:conf/ics/WangCHT09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xgze2dkp7rbyjd7tpjw2fleorq">fatcat:xgze2dkp7rbyjd7tpjw2fleorq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810151137/http://staff.ustc.edu.cn/~bhua/publications/ICS09.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/86/85/868559c1794ea6f0d9a6ab0383c69e3b3f04acad.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1542275.1542307"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Task Partitioning for Multi-core Network Processors [chapter]

Robert Ennals, Richard Sharp, Alan Mycroft
<span title="">2005</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
The instance we attack concerns the domain of packet processing applications such as Internet routers, firewalls and similar network devices.  ...  The parallel hardware architectures we target are Network Processors (NPs) [1, 6, 10, 23]: specialised programmable chips designed for high-speed packet processing.  ...  Acknowledgements This research was supported by (UK) EPSRC grant GR/S68941: "High-Level Languages for Network Processors".  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-31985-6_6">doi:10.1007/978-3-540-31985-6_6</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/t4vwujjojzgcbpeupigcq5x3xe">fatcat:t4vwujjojzgcbpeupigcq5x3xe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20131125062104/http://www.cl.cam.ac.uk:80/~am21/papers/cc05.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0a/b9/0ab921489e0a87fd051b9edf25a579720ece4b0f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-31985-6_6"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

FEADS: A Framework for Exploring the Application Design Space on Network Processors

Rajani Pai, R. Govindarajan
<span title="2007-01-03">2007</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6ni4hdyv7zdtzjxnzscp53l5ry" style="color: black;">International journal of parallel programming</a> </i> &nbsp;
This work proposes a novel framework, called FEADS, for automating the task of application partitioning and scheduling for network processors.  ...  To evaluate dynamic performance metrics such as throughput and resource utilization under realistic workloads, FEADS automatically generates a Petri net (PN) which models the application, architectural  ...  The application was partitioned at the logical cutting points revealed by the application, such as packet receive, header processing, and packet transmit.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10766-006-0023-0">doi:10.1007/s10766-006-0023-0</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/us55xq6qjrfuff56pwbqqr25ym">fatcat:us55xq6qjrfuff56pwbqqr25ym</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808170453/http://www.serc.iisc.ernet.in/~govind/papers/IJPP07-RajaniGov.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/86/f2/86f2b8d9d30cafd6b349cad295de10b10799da5e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10766-006-0023-0"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li, Omar Hammami
<span title="">2009</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yumlw7fbzbevvi2nz62kksdpwu" style="color: black;">International Journal of Reconfigurable Computing</a> </i> &nbsp;
An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution.  ...  And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation.  ...  An automatic design flow is proposed for data parallel and pipelined signal processing applications on embedded multiprocessor with NoC for cryptographic application TDES.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2009/631490">doi:10.1155/2009/631490</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/kcrbtxmc7jgd3jptwwrxqcuqf4">fatcat:kcrbtxmc7jgd3jptwwrxqcuqf4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200208171122/http://downloads.hindawi.com/journals/ijrc/2009/631490.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/19/fc/19fc50a8f9f60c7267699d16631c13153b0d4280.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2009/631490"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

A Throughput-Driven Task Creation and Mapping for Network Processors [chapter]

Lixia Liu, Xiao-Feng Li, Michael Chen, Roy D. C. Ju
<span title="">2007</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
Network processors are programmable devices that can process packets at a high speed.  ...  We propose a throughput cost model to guide the task creation and mapping with the objective of both minimizing the number of stages in the processing pipeline and maximizing the average throughput of  ...  We also appreciate the reviewers for their helpful feedback.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-69338-3_16">doi:10.1007/978-3-540-69338-3_16</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ztoeaw5zfjd3rcp6fswxroi5we">fatcat:ztoeaw5zfjd3rcp6fswxroi5we</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20160214165345/http://people.apache.org/~xli/papers/hipeac07-task-mapping-for-NPU.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1d/3a/1d3a39f42c19432606542c9e337709e5e45d7bcb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-69338-3_16"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

Zachary K. Baker, Viktor K. Prasanna
<span title="">2006</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/okrr6mjegfbtbjrfrxtci54s6i" style="color: black;">IEEE Transactions on Dependable and Secure Computing</a> </i> &nbsp;
This paper presents a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology, and tree-based lookahead architectures.  ...  Intrusion detection for network security is a compute-intensive application demanding high system performance.  ...  architectures automatically by our tool.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tdsc.2006.44">doi:10.1109/tdsc.2006.44</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ksodzwdcnzf5tmsrxqp66rsghy">fatcat:ksodzwdcnzf5tmsrxqp66rsghy</a> </span>
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Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs [chapter]

Zachary K. Baker, Viktor K. Prasanna
<span title="">2004</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
This paper presents a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology, and tree-based lookahead architectures.  ...  Intrusion detection for network security is a compute-intensive application demanding high system performance.  ...  architectures automatically by our tool.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-30117-2_33">doi:10.1007/978-3-540-30117-2_33</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dnwyebtmbvelxb34bmr6grdtdq">fatcat:dnwyebtmbvelxb34bmr6grdtdq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060721182928/http://halcyon.usc.edu:80/~zbaker/zbakerFPL.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/af/98/af98e2b9ab35a488cd90a24339ba402be57f5688.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-30117-2_33"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Programming challenges in network processor deployment

Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
<span title="">2003</span> <i title="ACM Press"> Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES &#39;03 </i> &nbsp;
Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implementation alternatives.  ...  The main observation of our study is that there is a critical lack of tools and methods that support an integrated approach to partitioning, scheduling and arbitration, and data transfer management for  ...  The C-5 has an architecture that expects the programmer to program in a pipelined approach to processing packets.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/951732.951735">doi:10.1145/951732.951735</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/a4avdoclkjdmtcdjut2kwt3uru">fatcat:a4avdoclkjdmtcdjut2kwt3uru</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20120913070924/http://www.eecs.berkeley.edu/IPRO/VIF/Papers/p178-kulkarni.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e9/e6/e9e66f9564fe6b51e8795636c5c9a9fa909925cd.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/951732.951735"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Programming challenges in network processor deployment

Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
<span title="">2003</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/h3qjmo5xyfe6fcrh4fogxmkkiq" style="color: black;">Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES &#39;03</a> </i> &nbsp;
Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implementation alternatives.  ...  The main observation of our study is that there is a critical lack of tools and methods that support an integrated approach to partitioning, scheduling and arbitration, and data transfer management for  ...  The C-5 has an architecture that expects the programmer to program in a pipelined approach to processing packets.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/951710.951735">doi:10.1145/951710.951735</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/cases/KulkarniGSK03.html">dblp:conf/cases/KulkarniGSK03</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6tvautuiifgxzn6ubxszec5sja">fatcat:6tvautuiifgxzn6ubxszec5sja</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20120913070924/http://www.eecs.berkeley.edu/IPRO/VIF/Papers/p178-kulkarni.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e9/e6/e9e66f9564fe6b51e8795636c5c9a9fa909925cd.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/951710.951735"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Infinity: A Scalable Infrastructure for In-Network Applications [article]

Marcelo Abranches, Karl Olson, Eric Keller
<span title="2021-03-26">2021</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
While programmable hardware enables customization of device operation, tailoring processing to finely tuned objectives, limited resources stifle much of the capability and scalability desired for future  ...  By forwarding both the processing need and associated data simultaneously we are able to scale operation with minimal overhead and delay, improving both capability and performance objectives for in-network  ...  For this, the application needs to specify a key upon which to partition any memory resources.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2103.14191v1">arXiv:2103.14191v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rauesqe73fcxjmjcd7imnfhsou">fatcat:rauesqe73fcxjmjcd7imnfhsou</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210330001941/https://arxiv.org/pdf/2103.14191v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/75/f1/75f177a1950b90e0609a388f726545a4d2bea22f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2103.14191v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud

Kemal Ebcioglu, Ismail San
<span title="2022-05-15">2022</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qfvmhupy5fb6tcrtb2orjpq5e4" style="color: black;">ACM Transactions on Reconfigurable Technology and Systems</a> </i> &nbsp;
We present a High Level Synthesis compiler that automatically obtains a multi-chip accelerator system from a single-threaded sequential C/C++ application.  ...  Therefore, software development for using the multi-chip accelerator hardware is simplified, but the multi-chip accelerator can exhibit extremely high parallelism.  ...  CONCLUSION We presented an application-speciic, high-performance approach for multi-FPGA accelerator system design starting from sequential code.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3507698">doi:10.1145/3507698</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/tizeillzrjhshngssrbtdunegm">fatcat:tizeillzrjhshngssrbtdunegm</a> </span>
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High-throughput linked-pattern matching for intrusion detection systems

Zachary K. Baker, Viktor K. Prasanna
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hqinhq4hgzfvfj7i5ayjeliple" style="color: black;">Proceedings of the 2005 symposium on Architecture for networking and communications systems - ANCS &#39;05</a> </i> &nbsp;
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented.  ...  Intrusion detection for network security is a compute-intensive application demanding high system performance.  ...  SUMMARY OF RESULTS This section presents results based on partitioning-only unary and tree architectures generated automatically by our tool.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1095890.1095918">doi:10.1145/1095890.1095918</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ancs/BakerP05.html">dblp:conf/ancs/BakerP05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6f3td5ayzbdxxhd7o563x5sc7e">fatcat:6f3td5ayzbdxxhd7o563x5sc7e</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809142535/https://static.aminer.org/pdf/PDF/000/286/014/an_efficient_pattern_match_architecture_for_production_systems_using_content.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/81/c7/81c7ec1aff287027615cef2fc7d4b7a8650171ea.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1095890.1095918"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Challenging the Stateless Quo of Programmable Switches

Nadeen Gebara, Alberto Lerner, Mingran Yang, Minlan Yu, Paolo Costa, Manya Ghobadi
<span title="2020-11-04">2020</span> <i title="ACM"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ec3stn5zango5b4zodjuij4olu" style="color: black;">Proceedings of the 19th ACM Workshop on Hot Topics in Networks</a> </i> &nbsp;
The characteristics and requirements of in-network applications, however, are quite different from those of packet protocols for which programmable switches were originally designed.  ...  In this paper, we describe the key obstacles to developing innetwork applications on PISA and propose rethinking the current switch architecture.  ...  As shown in Fig. 1 , the processing pipeline starts with a programmable parser that extracts the packet header fields required for the program execution [18] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3422604.3425928">doi:10.1145/3422604.3425928</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/hotnets/GebaraLYYCG20.html">dblp:conf/hotnets/GebaraLYYCG20</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/a3yjnkkhnnapzk6g6v7kwpap6a">fatcat:a3yjnkkhnnapzk6g6v7kwpap6a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210716074335/http://doc.rero.ch/record/330492/files/2020_Cudre-Mauroux_Challenging.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c4/a7/c4a723db7dde8595774041fc9ac9a38d01f6e4b9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3422604.3425928"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>
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