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Automatically generating instruction selectors using declarative machine descriptions
2010
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '10
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By generating the instruction selector from declarative machine descriptions we have (a) made it unnecessary for one person to be both a compiler expert and a machine expert, and (b) made creating an optimizing ...
Moreover, a critical component of the back end-the instruction selector-must be written by a person who is expert in both the compiler's intermediate code and the target machine's instruction set. ...
technique, an instruction selector is generated automatically from declarative machine descriptions. ...
doi:10.1145/1706299.1706346
dblp:conf/popl/DiasR10
fatcat:ndew7fwwgrertkusk4msjo3kz4
Automatically generating instruction selectors using declarative machine descriptions
2010
SIGPLAN notices
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By generating the instruction selector from declarative machine descriptions we have (a) made it unnecessary for one person to be both a compiler expert and a machine expert, and (b) made creating an optimizing ...
Moreover, a critical component of the back end-the instruction selector-must be written by a person who is expert in both the compiler's intermediate code and the target machine's instruction set. ...
technique, an instruction selector is generated automatically from declarative machine descriptions. ...
doi:10.1145/1707801.1706346
fatcat:ez544azoevcbphmceyner2lfkq
ACCGen: An Automatic ArchC Compiler Generator
2012
2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing
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In this work, we present ACCGen, an automatic Compiler Generator for ArchC, the missing link on the automatic generation of compiler toolchains for ArchC. ...
ArchC is an "Architecture Description Language" (ADL) and a set of tools that can be leveraged to automatically build SoC simulators based on high-level system models, enabling easy and fast design space ...
They propose to ease the work of compiler retargeting by automatically generating instruction selector for the C framework. ...
doi:10.1109/sbac-pad.2012.33
dblp:conf/sbac-pad/AulerCB12
fatcat:cliw4wd54nfm3ogzhkhwbubeyi
On the formal definition of PL/I
1968
Proceedings of the April 30--May 2, 1968, spring joint computer conference on - AFIPS '68 (Spring)
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I 371 The generation-list of b x contains only one element, the variable X having been declared AUTOMATIC. ...
Each instruction is deleted from the control after it has been executed. A form of the control tree using specific selectors is used to allow the evaluation of arguments of an instruction. ...
doi:10.1145/1468075.1468130
dblp:conf/afips/Bandat68
fatcat:hxgvpbfchvbt3khfgox5yqktbi
Compiler generation from structural architecture descriptions
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
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In this work we present a new structural architecture description language (ADL) that is used to derive the architecture dependent components of a compiler backend -most notably an instruction selector ...
A very promising approach is to model the target architecture using a dedicated description language that is rich enough to generate hardware components and the required tool chain, e.g., assembler, linker ...
The Trimaran compiler uses the MDes [14] machine description language to automatically customize the register allocator and instruction scheduler. ...
doi:10.1145/1289881.1289886
dblp:conf/cases/BrandnerEK07
fatcat:jhuo57km2jhkvovguo7ks7xuq4
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
2006
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology
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compiler, assembler, linker, and instruction-set simulator, can be automatically generated. ...
Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C ...
The instruction set information is extracted from the Register-Transfer Level (RTL) module netlist for use in code selector generation [4] . ...
doi:10.1007/s11265-006-7273-3
fatcat:2vj3liwr6ba6np57yccalei4ju
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
[chapter]
2004
Lecture Notes in Computer Science
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compiler, assembler, linker, and instruction-set simulator, can be automatically generated. ...
Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C ...
The instruction set information is extracted from the Register-Transfer Level (RTL) module netlist for use in code selector generation [4] . ...
doi:10.1007/978-3-540-27776-7_48
fatcat:lmvtrui7czddvcnrxsa5fl7iaq
Survey on Instruction Selection: An Extensive and Modern Literature Review
[article]
2013
arXiv
pre-print
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The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. ...
Hence instruction selection is a crucial part of efficient code generation. ...
[11, 12] -or generated automatically from a machine-specific description file. ...
arXiv:1306.4898v2
fatcat:pm6wvltmsjdznkhghvw4lxaq2m
Knowledge-based media coordination in intelligent user interfaces
[chapter]
1991
Lecture Notes in Computer Science
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We describe the architecture of the knowledge-based presentation system WIP which guarantees a design process with a large degree of freedom that can be used to tailor the presentation to suit the specific ...
In WIP, decisions of the language generator may influence graphics generation and graphical constraints may sometimes force decisions in the language production process. ...
Used by permission of the Association for Computational Linguistics; copies of the publication from which this material is derived can be obtained from Dr. Donald E. ...
doi:10.1007/3-540-54712-6_213
fatcat:rksmp44a6fa5ncnjquone4a5si
On the integration of Smalltalk and Java
2012
Proceedings of the International Workshop on Smalltalk Technologies - IWST '12
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Using techniques described in this paper, the programmer can call Java code from Smalltalk using standard Smalltalk idioms while the semantics of each language remains preserved. ...
We present STX:LIBJAVA -an implementation of Java virtual machine within Smalltalk/X -as a validation of our approach. ...
An example of accessing Java fields from Smalltalk Accessor methods are generated only for Java fields declared as public. If the field is declared as final, only getter method is generated. ...
doi:10.1145/2448963.2448968
dblp:conf/iwst/HlopkoKVG12
fatcat:qxmhxeh4f5fmfaipmbzivj67si
Effective compiler generation by architecture description
2006
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers and tool support for embedded systems - LCTES '06
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Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. ...
From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. ...
Conclusion In this paper, we have presented an Architecture Description Language for compiler generation that allows the generation of an instruction selector, a register allocator and an instruction scheduler ...
doi:10.1145/1134650.1134671
dblp:conf/lctrts/FarfelederKSB06
fatcat:a57pdprmkbeozk4jfmwzbxll4q
Effective compiler generation by architecture description
2006
SIGPLAN notices
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The file type is application/pdf.
Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. ...
From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. ...
Conclusion In this paper, we have presented an Architecture Description Language for compiler generation that allows the generation of an instruction selector, a register allocator and an instruction scheduler ...
doi:10.1145/1159974.1134671
fatcat:yanz6oia2fhdtm25l32fokvuba
Resourceable, retargetable, modular instruction selection using a machine-independent, type-based tiling of low-level intermediate code
2011
SIGPLAN notices
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Retargeting effort is further reduced by applying an earlier result which generates the machine-dependent implementation of our tileset automatically from a declarative description of instructions' semantics ...
Because the tiler is the part of the instruction selector that is most difficult to reason about, our technique makes it possible to retarget an instruction selector with significantly less effort than ...
declarative descriptions of the target-machine semantics. ...
doi:10.1145/1925844.1926451
fatcat:uwvtms62xrfcthpnt3ix2kgcwu
Resourceable, retargetable, modular instruction selection using a machine-independent, type-based tiling of low-level intermediate code
2011
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '11
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Retargeting effort is further reduced by applying an earlier result which generates the machine-dependent implementation of our tileset automatically from a declarative description of instructions' semantics ...
Because the tiler is the part of the instruction selector that is most difficult to reason about, our technique makes it possible to retarget an instruction selector with significantly less effort than ...
declarative descriptions of the target-machine semantics. ...
doi:10.1145/1926385.1926451
dblp:conf/popl/RamseyD11
fatcat:p7mzkmzxpbentnid4gocpzx6s4
A new term representation method for prolog
1998
The Journal of Logic Programming
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Based upon the mode declaration (in/+, out/A, and in_out/?), structure arguments can be classified into selectors and constructors. ...
In general, the code of a selector is executed under the current environment without delay--this is guaranteed by its input mode. Example 2 (Unification Code Generation). ...
doi:10.1016/s0743-1066(97)00062-9
fatcat:n4djeywvdjcmnem5b34awbv2py
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