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Automatic verification of pipelined microprocessor control
[chapter]
1994
Lecture Notes in Computer Science
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We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. ...
Empirical results include the verification of a pipelined implementation of a subset of the DLX architecture. ...
As a result, one verification run can check the control logic of pipelines with any combination of values for these parameters. ...
doi:10.1007/3-540-58179-0_44
fatcat:yowigfiwzjhrnpjco4z2io56jq
Automatic verification of pipelined microprocessors
1994
Proceedings of the 31st annual conference on Design automation conference - DAC '94
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In this paper, we present a methodology which allows for the verification of a specific class of synchronous machines, namely pipelined microprocessors. ...
We characterize the pipelined and unpipelined microprocessors as definite machines (i.e. a machine in which for some constant k, the output of the machine depends only on the last k inputs) for verification ...
Pipelined Microprocessors with fixed k In this section we consider verification of pipelined microprocessors with fixed k. ...
doi:10.1145/196244.196577
dblp:conf/dac/BhagwatiD94
fatcat:ruzgdeilirb7xolgrba24hjo2e
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
2008
2008 IEEE/ACM International Conference on Computer-Aided Design
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The result shows that the PEVT-SoC effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. ...
This paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the OCB. ...
In ARM7, it is achieved by gating clock controlled by the BIU. In LEON2, it is achieved by disabling the enable signal of the pipeline register. ...
doi:10.1109/iccad.2008.4681600
dblp:conf/iccad/YangZH08
fatcat:pz27f6tkxrcpxl2xxhx3ayyfka
A new verification methodology for complex pipeline behavior
2001
Proceedings of the 38th conference on Design automation - DAC '01
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A new test program generation tool, mVpGen, is developed for verifying pipeline design of microprocessors. ...
of a real microprocessor design and complex bugs that remained hidden in the RTL descriptions are detected. ...
Methods of automatically generating test cases, pipeline models, and verification programs are also mentioned in section 3. ...
doi:10.1145/378239.379072
dblp:conf/dac/KohnoM01
fatcat:hehv3haet5a7racw6pci3uyj3q
Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description
2012
2012 13th International Workshop on Microprocessor Test and Verification (MTV)
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The paper proposes an automated approach with a formal basis designed for checking correspondence between an RTL implementation of a microprocessor and a description of its instruction set architecture ...
The main idea is to use bounded model checking to check that the output produced by automatically derived RTL and ISA models of a given processor are the same for each instruction and each possible input ...
Most work on automated formal verification of pipelined microprocessors based on BMC and SAT solvers can be separated in two main branches: verification of the microprocessor wrt. general properties and ...
doi:10.1109/mtv.2012.19
dblp:conf/mtv/CharvatSV12
fatcat:tx5hiqdq3renjnp2o3diolxpdy
Automatic verification of external interrupt behaviors for microprocessor design
2007
Proceedings - Design Automation Conference
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PEVT has been applied to the verification of an academic implementation of ARM7 microprocessor core, which has had a SoC test chip and software porting including MP3 decoder and uC-OSII. ...
This paper proposes a CAD tool, called PEVT, to verify the external interrupt behaviors of microprocessors. ...
It defines the pipeline stages of microprocessor. For example, ARM7 is a three stage microprocessor including fetch, decode and execution stage. ...
doi:10.1145/1278480.1278701
dblp:conf/dac/YangHH07
fatcat:qmam2kslkjeatgqazlxhecg2kq
A methodology for validation of microprocessors using symbolic simulation
2005
International Journal of Embedded Systems
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We applied our methodology for property checking as well as equivalence checking of microprocessors. ...
., Krishnamurthy, N. and Abadir, M. (2005) 'A methodology for validation of microprocessors using symbolic simulation', Int. ...
We would like to acknowledge the members of the ACES laboratory for their inputs. ...
doi:10.1504/ijes.2005.008805
fatcat:dhd3uvfm2nbynihv4jtk2arss4
Coverage-directed verification of microprocessor units based on cycle-accurate contract specifications
2008
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)
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In this paper we describe a method for simulationbased verification of microprocessor units based on cycle-accurate contract specifications. ...
Test sequence generation is based on traversal of FSM constructed automatically from specifications and test coverage definition. ...
Now we are planning to generalize our approach for branching pipelines, pipelines with cycles, etc. ...
doi:10.1109/ewdts.2008.5580153
dblp:conf/ewdts/Kamkin08
fatcat:y4pykf7idbcffilbxsvmhiqmoi
High-level test generation for design verification of pipelined microprocessors
1999
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99
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This paper addresses test generation for design verification of pipelined microprocessors. ...
We have implemented the proposed algorithm and used it to generate verification tests for design errors in the datapath of a representative pipelined microprocessor. ...
CONCLUSIONS We are developing a system for automatically generating test sequences for design verification of pipelined microprocessors. ...
doi:10.1145/309847.309912
dblp:conf/dac/CampenhoutMH99
fatcat:zc737xefcndxbhnvtgedgu47my
A scalable formal verification methodology for pipelined microprocessors
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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We describe a novel, formal verification technique for proving the correctness of a pipelined microprocessor that focuses specifically on pipeline control logic. ...
We present experimental results from the formal verification of a DLX five-stage pipeline using our technique. ...
LHS Equation RHS
Conclusions We have presented a verification methodology that specifically targets the pipeline control logic of a microprocessor. ...
doi:10.1145/240518.240624
dblp:conf/dac/LevittO96
fatcat:gluhc4w3vba27hfdmsvz2v6sje
A correctness model for pipelined microprocessors
[chapter]
1995
Lecture Notes in Computer Science
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What does it mean for an instruction pipeline to be correct? We recently completed the specification and verification of a pipelined microprocessor called UINTA. ...
This paper presents the specification, describes the verification, and discusses the effect of pipelining on the correctness model. ...
This paper presents the verification of a pipelined microprocessor called UINTA. UINTA has a five stage pipeline which presents data and control hazards (there are no structural hazards). ...
doi:10.1007/3-540-59047-1_41
fatcat:2txkiwrelvb4pgn2fkvkrydrbm
Automatic generation of invariants in processor verification
[chapter]
1996
Lecture Notes in Computer Science
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A central task in formal verification is the definition of invariants, which characterize the reachable states of the system. When a system is finitestate, invariants can be discovered automatically. ...
Although the method is simple, it discovered 6 out of 7 of the invariants needed for verification of the CPU of the processor design, and 28 out of 72 invariants needed for verification of the memory system ...
The authors also wish to thank Robert Jones for his help and advice in preparing the final revision of the paper. ...
doi:10.1007/bfb0031822
fatcat:jvr3amwksvdpzkn45wct3pds5a
Effective theorem proving for hardware verification
[chapter]
1995
Lecture Notes in Computer Science
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They are applied to several examples including an N-bit adder, the Saxe pipelined processor, and the benchmark Tamarack microprocessor design. ...
We describe an approach for enhancing the effectiveness of theorem provers for hardware verification through the use of efficient automatic procedures for rewriting, arithmetic and equality reasoning, ...
John Rushby provided a great deal of support and encouragement for this work and supplied detailed comments on drafts of this paper. ...
doi:10.1007/3-540-59047-1_50
fatcat:zwwryahpejavfleqthleuefjjq
Verifying correct pipeline implementation for microprocessors
1997
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97
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We introduce a general, automatic verification technique for pipelined designs. The technique is based on a scalable, formal methodology for analysing pipelines. ...
Introduction Even with improved verification techniques, formal verification of entire systems such as a microprocessor design is likely to remain an intractable problem. ...
Conclusions We have described an automatic technique based on unpipelining for verifying microprocessor pipelines. ...
doi:10.1109/iccad.1997.643402
dblp:conf/iccad/LevittO97
fatcat:nitc4acwcjd3xd5hbpliv62b6u
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations
[chapter]
2001
Lecture Notes in Computer Science
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EVC has been used for the automatic formal verification of pipelined, superscalar, and VLIW microprocessors. ...
The logic expresses correctness of high-level microprocessors. ...
Introduction Formal verification of microprocessors has historically required extensive manual intervention. ...
doi:10.1007/3-540-44585-4_20
fatcat:2q4gugfj7bbk3pzbsh6hbxhlfi
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