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Automatic translation of C/C++ parallel code into synchronous formalism using an SSA intermediate form

Loïc Besnard, Thierry Gautier, Matthieu Moy, Jean-Pierre Talpin, Kenneth Johnson, Florence Maraninchi
2009 Electronic Communications of the EASST  
We present an approach for the translation of imperative code (like C, C++) into the synchronous formalism Signal, in order to use a model-checker to verify properties on the source code.  ...  The translation uses SSA as an intermediate formalism, and the GCC compiler as a front-end.  ...  Converting C/C++ into Ssa: The first step of the translation scheme consists in converting C/C++ models into the Ssa form.  ... 
doi:10.14279/tuj.eceasst.23.312 dblp:journals/eceasst/BesnardGMTJM09 fatcat:vhc7k6mfijfazmwktr5s4pwpgm

Interpretation of AADL Behavior Annex into Synchronous Formalism Using SSA

Yue Ma, Jean-Pierre Talpin, Thierry Gautier
2010 2010 10th IEEE International Conference on Computer and Information Technology  
We present an approach for this transformation using SSA as an intermediate formalism. This interpretation minimizes introducing new state variables and transitions.  ...  It introduces an effective method for transforming a behavior specification consisting of transitions and actions into a set of synchronous equations.  ...  Our approach and tools are based on the studies and experimental results on the translation of C/C++ parallel codes into synchronous formalism using SSA transformation [10] .  ... 
doi:10.1109/cit.2010.406 dblp:conf/IEEEcit/MaTG10 fatcat:bvkyrfmzcfbzvfee7ahc7vrje4

AMDA: Matching the Model-Driven-Architecture's Goals Using Extended Automata as a Common Model for Design and Execution

D. Dayan, R. Kaplinsky, A. Wiesen, S. Bloch
2007 IEEE International Conference on Software-Science, Technology & Engineering (SwSTE'07)  
We propose AMDA (Automata based MDA), a method based on the use of parallel automata, which can be a common tool for building a PIM from UML diagrams (including OCL) and transforming the PIM to PSM automata  ...  Each platform would then have a mechanism to execute the translated code.  ...  This PIM software layer will have two objectives: a) it will be an intermediate translation of the UML Model of the application, similar for instance to the "byte code" which is an intermediate translation  ... 
doi:10.1109/swste.2007.13 dblp:conf/swste/DayanKWB07 fatcat:pq4qwiuvwbbnpjkikdldawz5dq

Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study

Jorn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickael Raulet
2008 2008 IEEE Workshop on Signal Processing Systems  
Concurrency and parallelism are very important aspects of embedded system design as we enter in the multicore era.  ...  Results on a real design case, a MPEG-4 Simple Profile decoder, show that systems obtained with the hardware code generator outperform the hand written VHDL version both in terms of performance and resource  ...  Goals and features of CAL language Ease of use CAL is a true programming language and not an intermediate format to automatically generate code.  ... 
doi:10.1109/sips.2008.4671777 dblp:conf/sips/JanneckMPRWR08 fatcat:ev5nhvqmunauzhjveqbzke2ehq

Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study

Ghislain Roquier, Matthieu Wipliez, Mickael Raulet, Jorn W. Janneck, Ian D. Miller, David B. Parlour
2008 2008 IEEE Workshop on Signal Processing Systems  
A decoder configuration is written in an XML dialect by connecting a set of CAL modules.  ...  This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model.  ...  Code size and number of files automatically generated for the IDCT CAL NL C C++ H Number of files 5 1 5 6 6 Code Size (SLOC) 131 25 324 386 107 MPEG4 SP MPEG4 Speed Code size decoderTable  ... 
doi:10.1109/sips.2008.4671776 dblp:conf/sips/RoquierWRJMP08 fatcat:r3eabufhavgzpasvetr3ixolgm

Modular Interpretation of Heterogeneous Modeling Diagrams into Synchronous Equations Using Static Single Assignment

Jean-Pierre Talpin, Julien Ouy, Thierry Gautier, Loïc Besnard, Alexandre Cortier
2010 2010 10th International Conference on Application of Concurrency to System Design  
schedule or mode blocks) into a set of synchronous equations.  ...  This article focuses on the essence and distinctive features of its behavioral or programming aspects : actions, flows and automata, for which we use the code generation infrastructure of the synchronous  ...  All other data-flow equations match an instruction of the intermediate SSA form and its control-flow point.  ... 
doi:10.1109/acsd.2010.14 dblp:conf/acsd/TalpinOGBC10 fatcat:fztzseplwba4bowgbql3qqgh54

A static verification framework for message passing in Go using behavioural types

Julien Lange, Nicholas Ng, Bernardo Toninho, Nobuko Yoshida
2018 Proceedings of the 40th International Conference on Software Engineering - ICSE '18  
the form of a behavioural type, a powerful process calculi typing discipline.  ...  We make use of our analysis to deploy a model and termination checking based verification of the inferred behavioural type that is suitable for a range of safety and liveness properties of Go programs,  ...  Specifically, we convert Go source code into a static single assignment (SSA) form which provides a fine-grained view of the concurrency primitives used in programs in a quasi-functional form [2] , enabling  ... 
doi:10.1145/3180155.3180157 dblp:conf/icse/LangeNTY18 fatcat:gseo6wzhjjeuzizixg5gr3olpu

HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description [article]

Kingshuk Majumder, Uday Bondhugula
2021 arXiv   pre-print
This paper introduces HIR, an MLIR-based intermediate representation (IR) to describe hardware accelerator designs.  ...  HIR's explicit schedules allow it to express fine-grained, synchronization-free parallelism and optimizations such as retiming and pipelining.  ...  This makes it easy to exploit fine grained parallelism available in the hardware. • We build a code generator that translates HIR into synthesizable Verilog.  ... 
arXiv:2103.00194v1 fatcat:vwv7jfr2ofgxjih7uamqxvv4xe

Reconfigurable video coding

Jörn W. Janneck, Marco Mattavelli, Mickael Raulet, Matthieu Wipliez
2010 Proceedings of the first annual ACM SIGMM conference on Multimedia systems - MMSys '10  
parallelism of the coding algorithm.  ...  of coding tools.  ...  The final phase of the translation process generates an RTL implementation (in Verilog) from a set of threads in SSA form.  ... 
doi:10.1145/1730836.1730864 dblp:conf/mmsys/JanneckMRW10 fatcat:5stvtb4ghfgtnezviir4qgffl4

A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking

Jean-Pierre Talpin, Paul Le Guernic, Sandeep Kumar Shukla, Rajesh Gupta
2005 International journal of parallel programming  
The type system is presented using a generic and language-independent static single assignment intermediate representation.  ...  We propose a framework based on a synchronous multi-clocked model of computation to support the inductive and compositional construction of scalable behavioral models of embedded systems engineered with  ...  Formal syntax. Imperative programs are represented in an intermediate form that is common to the TAC and SSA IRs of GCC which provides language-independence and local optimization.  ... 
doi:10.1007/s10766-005-8907-y fatcat:gn4qxocw2nbnbguhhvsiddcu4q

The hArtes Tool Chain [chapter]

Koen Bertels, Ariano Lattanzi, Emanuele Ciavattini, Ferruccio Bettarelli, Maria Teresa Chiaradia, Raffaele Nutricato, Alberto Morea, Anna Antola, Fabrizio Ferrandi, Marco Lattuada, Christian Pilato, Donatella Sciuto (+10 others)
2012 Hardware/Software Co-design for Heterogeneous Multi-core Platforms  
The code is transformed into static single assignment (SSA) form; 2. Scalar replacement is performed.  ...  Thanks to the fact that scalar SSA-form variables are directly embedded into the GIMPLE code, if different SSA versions of the same scalar variable are dumped back in the produced source code, they are  ... 
doi:10.1007/978-94-007-1406-9_2 fatcat:izopdxmxxnegnotxjvvcqmle3i

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

Ruirui Gu, Jonathan Piat, Mickael Raulet, Jorn W. Janneck, Shuvra S. Bhattacharyya
2010 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
This paper proposes an automatic design flow from userfriendly design to efficient implementation of video processing systems.  ...  Our approach, which is a novel integration of three complementary dataflow toolsthe CAL parser, TDP, and CAL2C -is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder.  ...  Intermediate Representation The Intermediate Representation (IR) used in Orcc is managed in the form of .jason files. The top-level structure in the Intermediate Representation is an actor.  ... 
doi:10.1109/dasip.2010.5706274 dblp:conf/dasip/GuPRJB10 fatcat:dc2ui2ya3nh7rauukzi3rnnjme

Automatically harnessing sparse acceleration

Philip Ginsbach, Bruce Collie, Michael F. P. O'Boyle
2020 Proceedings of the 29th International Conference on Compiler Construction  
The LiLAC-enabled compiler uses this to insert appropriate library routines without source code changes.  ...  Moreover, libraries tie programs into vendor-specific software and hardware ecosystems, creating non-portable code.  ...  The result is an LLVM optimization pass that is available when linking LLVM with the clang C/C++ compiler. This pass performs the discovery of linear algebra code and the insertion of harness calls.  ... 
doi:10.1145/3377555.3377893 dblp:conf/cc/GinsbachCO20 fatcat:wf6utlth6na7ddronimzit5xzq

Divergence Analysis and Optimizations

Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintao Pereira, Wagner Meira Jr.
2011 2011 International Conference on Parallel Architectures and Compilation Techniques  
This analysis is useful in three different ways: it improves the translation of SIMD code to non-SIMD CPUs, it helps developers to manually improve their SIMD applications, and it also guides the compiler  ...  Our automatic optimization adds a 3% speed-up onto parallel quicksort, a heavily optimized benchmark. Our manual optimizations extend this number to over 10%. • two arrays of instructions, T =  ...  Acknowledgment: we thank Sylvain Collange and Marcelo D'Amorim for reviewing a draft of this paper, and Jacques Cohen for pointing the Smith-Waterman algorithm to us.  ... 
doi:10.1109/pact.2011.63 dblp:conf/IEEEpact/CoutinhoSPM11 fatcat:yw6lopa7tngrhgntbdprunlpne

Compiling Scilab to high performance embedded multicore systems

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Juergen Becker, Gerard Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias (+5 others)
2013 Microprocessors and microsystems  
This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different  ...  The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of  ...  be used by our auto-vectorization approach within fine-grain parallelism extraction and (3) for translating the ALMA Intermediate Representation (IR) to C code during parallel code generation.  ... 
doi:10.1016/j.micpro.2013.07.004 fatcat:pdh6kpwp25galdrdtvpv45l2cy
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