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Design flow for embedded FPGAs based on a flexible architecture template

B. Neumann, T. von Sydow, H. Blume, T. G. Noll
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
First commercial products combining a general purpose processor core and an embedded FPGA recently emerged (e.g. Stretch S6000 [2], Menta eFPGAaugmented CPUs [3] ).  ...  For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general purpose processors [1] .  ...  For an embedded FPGA used as configurable accelerator, however, the requirements concerning the provided resources are often well defined and much narrower than for discrete "general purpose" FPGAs.  ... 
doi:10.1145/1403375.1403391 fatcat:4zu3k2ej7vg5tn6omsktbvwzpe

VLSI DESIGN PROCESS FOR LOW POWER DESIGN METHODOLOGY USING RECONFIGURABLE FPGA

R. Rajendra Prasad .
2012 International Journal of Research in Engineering and Technology  
For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general-purpose processors.  ...  Since changes in standards or algorithms can change the demands on the accelerators, an attractive alternative to highly customized VLSI macros is suggested with the usage of reconfigurable embedded FPGAs  ...  For an embedded FPGA used as configurable accelerator, however, the requirements concerning the provided resources are often well defined and much narrower than for discrete or "general purpose" FPGAs.  ... 
doi:10.15623/ijret.2012.0103053 fatcat:yuuqiq6murapnlm3ivcewoa2qi

A Review on Embedded FPGAs Architectures and Configuration Tools

2019 Turkish Journal of Electrical Engineering and Computer Sciences  
In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance  ...  Key words: Embedded field programmable gate array, computer aided design tools, mesh-based architecture, tree-based architecture, field programmable gate array performance  ...  Acknowledgment This work is supported by Computer and Embedded Systems Laboratory and Digital Research Center of Sfax.  ... 
doi:10.3906/elk-1901-193 fatcat:kimby27rrbfyte4t2bh3lqtg3q

A hybrid ASIC and FPGA architecture

Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
This background data indicates that there are advantages to using standard ASICs and FPGAs for many applications, but technical and financial considerations are increasingly driving the need for a hybrid  ...  Introduction This paper introduces a new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx, and highlights some of the design challenges this offers for  ...  This requires a re-layout of the FPGA cores, which were originally designed for a standard product with 9 levels of metal.  ... 
doi:10.1145/774572.774600 dblp:conf/iccad/ZuchowskiRGDCT02 fatcat:xciuw3kxrnezdpahugnndpi3mm

A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory

M. Borgatti, P. L. Rolandi, L. Calì, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles
2003 Proceedings of the 40th conference on Design automation - DAC '03  
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets imagevoice processing and recognition applications.  ...  Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s.  ...  size 8.2 mm2 Customizable I/O 24 general-purpose inputs 24 general-purpose outputs (tri-state) 8 general-purpose bidirs Power supply 2.7-3.6V (I/O), 1.6-2.0V (core)  ... 
doi:10.1145/776004.776007 fatcat:kwkr5nmlrrc35ciztgfkj24x7q

A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory

M. Borgatti, P. L. Rolandi, L. Calì, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles
2003 Proceedings of the 40th conference on Design automation - DAC '03  
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets imagevoice processing and recognition applications.  ...  Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s.  ...  size 8.2 mm2 Customizable I/O 24 general-purpose inputs 24 general-purpose outputs (tri-state) 8 general-purpose bidirs Power supply 2.7-3.6V (I/O), 1.6-2.0V (core)  ... 
doi:10.1145/775832.776007 dblp:conf/dac/BorgattiCSFILMPPR03 fatcat:4m6go2krffe4tj5j2zg3eqm7kq

Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic

T. Sydow, B. Neumann, H. Blume, T. Noll
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed.  ...  Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while highthroughput digital signal processing algorithms can be realised efficiently.  ...  This is achieved using a flexible datapath generator (DPG) described in [7] . The DPG was originally designed for automatic layout of highly regular datapaths.  ... 
doi:10.1109/asap.2006.56 dblp:conf/asap/SydowNBN06 fatcat:mazuyfkv3zegpf7xmdv3fkit2y

Using embedded FPGAs for SoC yield improvement

M. Abramovici, C. Stroud, M. Emmert
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC.  ...  We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with  ...  BIST-Cores For a BIST-core, its BIST logic may be moved from the core to the embedded FPGA, as illustrated in Figure 12 .  ... 
doi:10.1109/dac.2002.1012717 fatcat:ov3bwhjztfghdc2i3ezbbhpuva

Using embedded FPGAs for SoC yield improvement

Miron Abramovici, Charles Stroud, Marty Emmert
2002 Proceedings - Design Automation Conference  
In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC.  ...  We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with  ...  BIST-Cores For a BIST-core, its BIST logic may be moved from the core to the embedded FPGA, as illustrated in Figure 12 .  ... 
doi:10.1145/513918.514099 dblp:conf/dac/AbramoviciSE02 fatcat:w3kkarh6fbbtxgk6hnf7fi66vu

Using embedded FPGAs for SoC yield improvement

Miron Abramovici, Charles Stroud, Marty Emmert
2002 Proceedings - Design Automation Conference  
In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC.  ...  We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with  ...  BIST-Cores For a BIST-core, its BIST logic may be moved from the core to the embedded FPGA, as illustrated in Figure 12 .  ... 
doi:10.1145/514097.514099 fatcat:wv5mqq6vnzfvpaakmhqdlo74au

Implementation of FPGA-Based Controller in Automatic Control System Platform for Launch Site

Li Tian Xiao, Meng Yuan Li, Wei Guo Wang, Ke Wen Hou, Yu Liang Li
2020 Procedia Computer Science  
The schemes include the board layout and design of the logic daughter card for the architecture of the FPGA-based controller.  ...  The schemes include the board layout and design of the logic daughter card for the architecture of the FPGA-based controller.  ...  Acknowledgments This work is funded by the project Autonomous Controllable on Intellectual Property for Control System in Launch Site (No.17R004N-D), partially sponsored by the Agreement JG-2017-1-001.  ... 
doi:10.1016/j.procs.2020.02.007 fatcat:o3flf4vcxrgcndsb7la4e5hiym

FPGA Circuit Synthesis of Accelerator Data-Parallel Programs

Barry Bond, Kerry Hammil, Lubomir Litchev, Satnam Singh
2010 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines  
We identify the subset of data-parallel descriptions that are supported by our system and explain how we track memory access patterns which allow us to generate efficient FPGA circuits. I.  ...  This paper describes the techniques used to describe and synthesize FPGA circuits expressed in a dataparallel domain specific language (DSL) called Accelerator.  ...  However, the FPGA target is off-line i.e. calling ToArray results in the generation of VHDL source code files plus .XCO files for Xilinx's Core Generator system for the instantiation of floating point  ... 
doi:10.1109/fccm.2010.51 dblp:conf/fccm/BondHLS10 fatcat:gaclnncikjbsfohxq2ghlfwjfy

Design, layout and verification of an FPGA using automated tools

Ian Kuon, Aaron Egier, Jonathan Rose
2005 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05  
Our aim is to demonstrate the feasibility of a CAD flow that uses an input FPGA architecture description to generate a layout that can be sent for fabrication.  ...  Through this architecture to layout process, we investigate the issues that are faced in the architecture selection, circuit design, layout and verification of such an automatically produced FPGA.  ...  Finally, we would like to thank NSERC and Altera for their generous funding of this project.  ... 
doi:10.1145/1046192.1046220 dblp:conf/fpga/KuonER05 fatcat:w6mpfglfbng4tdnj5ckhuvpxiq

FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI
2013 IEICE transactions on information and systems  
By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream.  ...  VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons.  ...  One SoC product can easily be used for different applications by implementing functions that need to be renewed frequently or customized on an embedded FPGA IP core.  ... 
doi:10.1587/transinf.e96.d.1602 fatcat:quem56ufirhpxma7ts23owiz7y

Managing Security in FPGA-Based Embedded Systems

Ted Huffmire, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy Levin, Thuy D. Nguyen, Cynthia Irvine
2008 IEEE Design & Test of Computers  
As they become more common in critical embedded systems, new techniques are necessary to manage security in FPGA designs.  ...  industry, for example, relies on FPGAs to control everything from the Joint Strike Fighter to the Mars Rover.  ...  Acknowledgments We thank the anonymous reviewers for their comments. This research was funded in part by National Science Foundation grant CNS-0524771 and NSF Career grant CCF-0448654.  ... 
doi:10.1109/mdt.2008.166 fatcat:geb3q2d3krf4pfetb4ncatdzlm
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