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Automated application acceleration using software to hardware transformation

Qiwei Jin, David B. Thomas, Wayne Luk
2009 2009 International Conference on Field-Programmable Technology  
A demonstration of this approach has been built for the C# language.  ...  This paper describes an approach that allows applications to be developed in a software language, while taking advantage of hardware by facilities that automatically transform such software programs for  ...  The support of J.P. Morgan Securities Limited is gratefully acknowledged.  ... 
doi:10.1109/fpt.2009.5377693 fatcat:7iujx3nspzaj7hg73hxiqsga6i

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Mostafa W. Numan, Braden J. Phillips, Gavin S. Puddy, Katrina Falkner
2020 IEEE Access  
DOMAIN-SPECIFIC LANGUAGE (DSL) FOR HLS 2C Although HLS tools are improving, the benefit delivered by an FPGA hardware accelerator still depends strongly on the system developers' hardware expertise.  ...  A DSL can be used to describe a domain-specific computing system at a higher level of abstraction than an HDL.  ... 
doi:10.1109/access.2020.3024098 fatcat:hk7s2deq6zgp5fnuwvm5k6jodu

Proposal of Automatic FPGA Offloading for Applications Loop Statements [article]

Yoji Yamato
2020 arXiv   pre-print
However, when using heterogeneous hardware other than CPUs, barriers of technical skills such as OpenCL are high.  ...  In this paper, I propose and evaluate an automatic extraction method of appropriate offload target loop statements of source code as the first step of offloading to FPGA.  ...  Performance results As an application where manual acceleration is often performed on FPGA, we confirmed automatic accelerations of time domain finite impulse response filter.  ... 
arXiv:2004.08548v1 fatcat:yuywyjk2irhkjpoiii4lp4xini

Programming Heterogeneous Systems from an Image Processing DSL [article]

Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, Mark Horowitz
2016 arXiv   pre-print
that uses this code to automatically create the accelerator along with the "glue" code needed for the user's application to access this hardware.  ...  We address this problem by extending the image processing language, Halide, so users can specify which portions of their applications should become hardware accelerators, and then we provide a compiler  ...  So, to further reduce the hardware knowledge a designer needs, researchers created domain specific languages (DSLs), which can embed microarchitecture knowledge for a specific application domain in the  ... 
arXiv:1610.09405v1 fatcat:p2qq2gcifnez7mtrswcl2h2vfy

Transparent Compiler and Runtime Specializations for Accelerating Managed Languages on FPGAs

Michail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos, Foivos S. Zakkak, Christos Kotselidis
2020 The Art, Science, and Engineering of Programming  
FPGAs are a subset of the most widely used co-processors, typically used for accelerating specific workloads due to their flexible hardware and energy-efficient characteristics.  ...  Developers who create their applications using high-level programming languages (e.g., Java, Python, etc.) are required to familiarize with a hardware description language (e.g., VHDL, Verilog) or recently  ...  Our work differs from all aforementioned frameworks since it: a) automatically and dynamically compiles Java programs onto optimized FPGA binary code, b) it does not require the use of hardware-specific  ... 
doi:10.22152/ fatcat:iele6rhz5bavphj733vpsyckci

Transparent hardware synthesis of Java for predictable large-scale distributed systems [article]

Ian Gray, Yu Chan, Jamie Garside, Neil Audsley, Andy Wellings
2015 arXiv   pre-print
Initial results show that the use of Java does not hamper hardware generation, and provides tight execution time estimates.  ...  Part of this work involves the automatic implementation of input Java code on FPGAs, both for speed and predictability.  ...  In all of these results we can see that the generated hardware has a specific latency value, rather than a range.  ... 
arXiv:1508.07142v1 fatcat:izfnahdd5zasnbt7tvrskj722u

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
2021 Journal of Signal Processing Systems  
Fletcher adds FPGA accelerators to the list of over eleven supported software languages.  ...  To deal with the hardware challenges, we present Arrow-specific components, providing easy-to-use, high-performance interfaces to accelerated kernels.  ...  To view a copy of this licence, visit http:// creativecommonshorg/licenses/by/4.0/.  ... 
doi:10.1007/s11265-021-01650-6 fatcat:5ranxhrntjcrtd77opsaz2e7da

Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs

Emanuele Del Sozzo, Davide Conficconi, Alberto Zeni, Mirko Salaris, Donatella Sciuto, Marco D. Santambrogio
2022 ACM Computing Surveys  
Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs), High-Level Synthesis (HLS) tools, and Domain-Specific Languages (DSLs).  ...  They are state-of-the-art for prototyping, telecommunications, embedded, and an emerging alternative for cloud-scale acceleration.  ...  ACKNOWLEDGEMENTS The authors are grateful for feedbacks from Reviewers and NECSTLab members, with a particular mention to A. Damiani, A. Parravicini, E. D'Arnese, F. Carloni, F. Peverelli, and R.  ... 
doi:10.1145/3532989 fatcat:nsk5lwvt3vba5fbxmaj7sgpwru

Computer assisted design and integration of FPGA accelerators in aerospace systems

Marco Lattuada, Fabrizio Ferrandi, Maxime Perrotin
2016 2016 IEEE Aerospace Conference  
To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating  ...  The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability.  ...  The authors proposed a new Domain Specific Language for describing the different components of an application targeting space systems and provided a framework to automatically generate the code to implement  ... 
doi:10.1109/aero.2016.7500675 fatcat:q4flq4y3trhgtnqpeflhimxa2i

Object-oriented domain specific compilers for programming FPGAs

O. Mencer, M. Platzner, M. Morf, M.J. Flynn
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Each domain-specific compiler is targeted at a very specific application domain, such as applications that accelerate Boolean satisfiability problems with BSAT, and applications which lend themselves for  ...  The key benefit of the presented domain specific compilers is a reduction of design time by orders of magnitude while keeping the optimal performance of hand-designed circuits.  ...  ACKNOWLEDGMENT The authors would like to acknowledge the contributions of many students, current and past, to the JHDL system.  ... 
doi:10.1109/92.920835 fatcat:qm53w6pj6fa3fjxnskuqjq6xta

HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description [article]

Kingshuk Majumder, Uday Bondhugula
2021 arXiv   pre-print
We believe that these are significant steps forward in the design of IRs for hardware synthesis and in equipping domain-specific languages with a productive and performing compilation path to custom hardware  ...  Though FPGAs are an ideal target for energy efficient custom accelerators, the difficulty of hardware design and the lack of vendor agnostic, standardized hardware compilation infrastructure has hindered  ...  use of specialized hardware accelerators.  ... 
arXiv:2103.00194v1 fatcat:vwv7jfr2ofgxjih7uamqxvv4xe

Deep Learning on FPGAs: Past, Present, and Future [article]

Griffin Lacey, Graham W. Taylor, Shawki Areibi
2016 arXiv   pre-print
This review takes a look at deep learning and FPGAs from a hardware acceleration perspective, identifying trends and innovations that make these technologies a natural fit, and motivates a discussion on  ...  While the current solution has been to use clusters of graphics processing units (GPU) as general purpose processors (GPGPU), the use of field programmable gate arrays (FPGA) provide an interesting alternative  ...  using hardware accelerators.  ... 
arXiv:1602.04283v1 fatcat:xffu7dm7ifbxjir7ivskhxozyi

AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms [article]

Yuke Wang, Boyuan Feng, Gushu Li, Lei Deng, Yuan Xie, Yufei Ding
2019 arXiv   pre-print
CPU and the hardware acceleration on the FPGA.  ...  Specifically, AccD provides a Domain-specific Language to unify distance-related algorithms effectively, and an optimizing compiler to reconcile the benefits from both the algorithmic optimization on the  ...  First, previous FPGA designs are generally built for specific distance-related algorithm and hardware.  ... 
arXiv:1908.11781v1 fatcat:qomhzsfycfcgtbki3paqmok6f4

Compiling high throughput network processors

Maysam Lavasani, Larry Dennison, Derek Chiou
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of FPGAs provide high performance, low power, and programmability  ...  Gorilla achieves high performance and low power through the use of FPGA-tailored parallelization techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms  ...  We use Gorilla to generate a family of network processors capable of handling almost all combinations of MPLS, IPv4, and IPv6 traffic at 200MPPS rate in a single FPGA.  ... 
doi:10.1145/2145694.2145709 dblp:conf/fpga/LavasaniDC12 fatcat:xdotup5uavc6hh5sqkkarttj6a

Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration

Lieu My Chuong, Yan Lin Aung, Siew-Kei Lam, Thambipillai Srikanthan, Lim Chai Soon
2011 2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming  
We present a design exploration framework that automatically compiles C applications to realize efficient custom coprocessor structures for hardware acceleration on the reconfigurable logic.  ...  Advancement in design tools is necessary to bridge the widening productivity gap between hardware design and software development in state-of-the-art Field Programmable Gate Arrays (FPGA).  ...  Altera C2H software is an EDA tool that is used for automatically translating algorithms written in ANSI-C into RTL codes so that they can be implemented as a hardware accelerator using Altera Quartus  ... 
doi:10.1109/paap.2011.70 dblp:conf/paap/ChuongALSL11 fatcat:rcn4sjaupncmxc46us5celqwmm
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