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Automatic formal verification for scheduled VLIW code

Xiushan Feng, Alan J. Hu
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
VLIW processors are attractive for many embedded applications, but VLIW code scheduling, whether by hand or by compiler, is extremely challenging.  ...  I implement these ideas into two prototype tools for verifying short sequences of assembly code for TI's C62x family of VLIW DSPs and Fujitsu's FR500 VLIW processor, and demonstrate the effectiveness of  ...  Such verification tools could automatically verify the functional equivalence of two pieces of VLIW assembly code.  ... 
doi:10.1145/513829.513844 dblp:conf/lctrts/FengH02 fatcat:cgw473q6rbbgvlbczahsn2q734

PICO: automatically designing custom computers

V. Kathail, S. Aditya, R. Schreiber, B. Ramakrishna Rau, D.C. Cronquist, M. Sivaraman
2002 Computer  
We thank Henk Corporaal for providing the code for the attractive GUI to his MOVE infrastructure, from which we Framework-based automation offers a powerful methodology for automating the design of complex  ...  processors and computer systems. developed PICO's GUI, and Wen-mei Hwu and his IMPACT group for providing Elcor's machineindependent front end.  ...  In addition to the RTL artifact, the constructor also generates an RTL testbench and memory simulation models for block-level RTL verification and a cycle-accurate C model to support system-level verification  ... 
doi:10.1109/mc.2002.1033026 fatcat:nqa5tazc5zfixew3lwznahgmne

Customizing Software Toolkits for Embedded Systems-on-Chip [chapter]

Ashok Halambi, Nikil Dutt, Alex Nicolau
2001 IFIP Advances in Information and Communication Technology  
This paper describes our Architecture Description Language (ADL) driven approach for customizing software toolkits.  ...  As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers  ...  After verification, the software toolkit is automatically generated to be used for software compilation and co-simulation of the hardware and software.  ... 
doi:10.1007/978-0-387-35409-5_9 fatcat:4ynfl3yzgrghbj2yiub6yamksu

Instruction scheduler generation for retargetable compilation

O. Wahlen, M. Hohenauer, R. Leupers, H. Meyr
2003 IEEE Design & Test of Computers  
Using virtual resources to automatically generate parts of a compiler's instruction scheduler from a formal processor description significantly reduces the overall scheduler generation time.  ...  We have developed a technique that improves compiler retargetability by automatically generating parts of the instruction scheduler from a formal architecture description.  ... 
doi:10.1109/mdt.2003.1173051 fatcat:yjdk2y4ndffmto3rpauo62myai

Automatic formal verification of DSP software

David W. Currie, Alan J. Hu, Sreeranga Rajan
2000 Proceedings of the 37th conference on Design automation - DAC '00  
DSPs (e.g. statically-scheduled, VLIW).  ...  This paper describes a novel formal verification approach for equivalence checking of small, assembly-language routines for digital signal processors (DSP).  ...  INTRODUCTION Software for digital signal processors (DSP) is a particularly promising area for automatic formal verification: DSPs have become ubiquitous as countless formerly analog application domains  ... 
doi:10.1145/337292.337339 dblp:conf/dac/CurrieHR00 fatcat:grohhw4vkrgqrj6yvg7cw5ei6q

EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability [chapter]

Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil Dutt, Alex Nicolau
2008 Design, Automation, and Test in Europe  
compiler scheduling.  ...  We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-on-Chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit.  ...  As with an HDL-based ASIC design flow, several benefits accrue from a language-based design methodology for embedded SOC exploration, including the ability to perform (formal) verification and consistency  ... 
doi:10.1007/978-1-4020-6488-3_3 fatcat:ts2yltlabnb3dgg4x63juiiqkq

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  On Merlot, multiple threads provide wider issue window beyond ordinal instruction level parallel (ILP) processors like superscalar or VLIW.  ...  Speculative multithreading has been proposed to remove this burden by automatic parallelization with compiler or object code conversion [1] [2] [3] .  ... 
doi:10.1145/581199.581223 fatcat:x36o4c62hbh7vaozjrpgrwzvte

A 52mW 1200MIPS compact DSP for multi-core media SoC

Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently.  ...  The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software  ...  The functional verification of the synthesized gate-level net-list is through the formal equivalence checking with the RTL model.  ... 
doi:10.1145/1118299.1118335 fatcat:b2xon6r5m5dbrekhazclcfqype

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  On Merlot, multiple threads provide wider issue window beyond ordinal instruction level parallel (ILP) processors like superscalar or VLIW.  ...  Speculative multithreading has been proposed to remove this burden by automatic parallelization with compiler or object code conversion [1] [2] [3] .  ... 
doi:10.1145/581220.581223 fatcat:ylogpwxrprhafgn6jc2acch3vy

Cutpoints for formal equivalence verification of embedded software

Xiushan Feng, Alan J. Hu
2005 Proceedings of the 5th ACM international conference on Embedded software - EMSOFT '05  
We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs, and our experiments show large improvements in runtime and memory usage.  ...  The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization.  ...  We thank the anonymous reviewers for encouraging us to try public, hand-tuned examples for our experiments and for suggesting several promising ideas for future work.  ... 
doi:10.1145/1086228.1086284 dblp:conf/emsoft/FengH05 fatcat:urjoxbeyvjdevb7a3hqahkuc2i

Modular Operational Semantic Specification of Transport Triggered Architectures [chapter]

Jon Mountjoy, Pieter Hartel, Henk Corporaal
1997 Hardware Description Languages and their Applications  
However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is  ...  The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult.  ...  ACKNOWLEDGEMENTS The authors thank Marcel Beemster, Hugh McEvoy and the referees for their comments which greatly improved the paper.  ... 
doi:10.1007/978-0-387-35064-6_22 fatcat:anelmdgqrbhl3mq6c5nclku4va

Correct and Efficient Accelerator Programming (Dagstuhl Seminar 13142)

Albert Cohen, Alastair F. Donaldson, Marieke Huisman, Joost-Pieter Katoen, Marc Herbstritt
2013 Dagstuhl Reports  
Accelerators present a serious challenge for software developers.  ...  Dagstuhl seminar was to bring together researchers from various sub-disciplines of computer science to brainstorm and discuss the theoretical foundations, design and implementation of techniques and tools for  ...  We use a tool to automatically annotate C code with species information where possible.  ... 
doi:10.4230/dagrep.3.4.17 dblp:journals/dagstuhl-reports/CohenDHK13 fatcat:4qiimr6nwfdibcj6nmhw4ml2pu

Functional validation of programmable architectures

P. Mishra, N. Dutt
2004 Euromicro Symposium on Digital System Design, 2004. DSD 2004.  
Traditional validation techniques employ different reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies  ...  Finally, the generated simulator and hardware models are also used for early exploration of programmable architectures.  ...  The specification (SPEC in Figure 5 ) for the formal verification is derived from the architecture description.  ... 
doi:10.1109/dsd.2004.1333253 dblp:conf/dsd/MishraD04 fatcat:ttnifepgbngxdmlknc2swikqpq

A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, H. Meyr
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Moreover, for architecture implementation, synthesizable hardware description language code can be derived, which can then be processed by standard synthesis tools.  ...  From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend.  ...  The approaches of Maril [10] as part of the Marion environment and a system for very long instruction word (VLIW) compilation [11] are both using latency annotation and reservation tables for code  ... 
doi:10.1109/43.959863 fatcat:dy5amg26prapdghj6a7b66j6c4

Architecture Description Languages for Retargetable Compilation [chapter]

Wei Qin, Sharad Malik
2002 The Compiler Design Handbook  
They are usually written for high quality proprietary compilers or developed for special architectures requiring non-standard code generation flow.  ...  The second and possibly more important need for this is in the design space exploration for the architecture and micro-architecture of the processor being developed.  ...  It also results in different requirements for the operation scheduler: for superscalar, the scheduler only needs to remove as many read-afterwrite(RAW) data hazards as possible; while for VLIW, the scheduler  ... 
doi:10.1201/9781420040579.ch14 fatcat:sa3eihqbqjdv3bzdh3wsuuyzaa
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