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Automatic verification of sequential circuit designs

E. M. Clarke, J. R. Burch, O. Grumberg, D. E. Long, K. L. McMillan, John Edwin Field, Peter Gray
1992 Philosophical Transactions of the Royal Society of London Series A Physical and Engineering Sciences  
Temporal logic model checking is a method for automatically deciding if a sequential circuit satisfies its specifications.  ...  The procedure has been used successfully in the past to find subtle errors in a number of non-trivial circuit designs.  ...  A path in M is an infinite sequence of states n = 50 5X ... such th at for every ie /V, R(st, 5i+1 Automatic verification of sequential circuit designs 111 5 . s\= E(<pU^) if and only if there exists  ... 
doi:10.1098/rsta.1992.0028 fatcat:pkrj3pof5jcjhn5uvgiishj6ay

Seqver : A Sequential Equivalence Verifier for Hardware Designs

Daher Kaiss, Silvian Goldenberg, Ziyad Hanna, Zurab Khasidashvili
2006 Computer Design (ICCD '99), IEEE International Conference on  
Automatic synchronization (reset) of sequential synchronous circuits is considered as one of the most challenging tasks in the domain of sequential equivalence verification.  ...  This paper addresses the problem of formal equivalence verification of hardware designs.  ...  Despite the fact that some methods for automatic mapping exit, most of this effort in custom designs is manual and thus time consuming.  ... 
doi:10.1109/iccd.2006.4380827 dblp:conf/iccd/KaissGK06 fatcat:zgreo3qsibfdvh2vxm67rww4pq

Formal verification of pipelined cryptographic circuits: A functional approach

Abir Bitat, Salah Merniz
2021 Informatica (Ljubljana, Tiskana izd.)  
This paper presents an automatic verification methodology for the pipelined cryptographic circuits using formal methods.  ...  poorly suited for formal verification.  ...  -The functional HDL used in our approach has some built-in tools that allow automatic formal verification of circuits.  ... 
doi:10.31449/inf.v45i4.3176 fatcat:53ridqhllfhpvmduujvdmqdi7i

An efficient design-for-verification technique for HDLs

Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
2001 Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01  
Abstraction Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process.  ...  By the help of those DFV points, the number of required test patterns to reach the same coverage can be greatly reduced especially for deep-sequential designs.  ...  Introduction Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process [1] .  ... 
doi:10.1145/370155.370291 dblp:conf/aspdac/LiuCJ01 fatcat:un3ogp6revd6xp7vno4if4g6q4

High capacity and automatic functional extraction tool for industrial VLSI circuit designs

Sasha Novakovsky, Shy Shyman, Ziyad Hanna
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
FEV-Extract employs a powerful hierarchical analysis procedure, and advanced and generic algorithms for automatic recognition of logical primitives, to cope with variety of circuit design styles and their  ...  In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation.  ...  Additional thanks go to the CAD infra structure group in Design Technology for the codevelopment of numerous algorithms and software modules needed in FEV-Extract implementation.  ... 
doi:10.1145/774572.774649 dblp:conf/iccad/NovakovskySH02 fatcat:cwpoovq3rfd7vbwvnw6zicembe

Experiences in Digital Circuit Design Courses: A Self-Study Platform for Learning Support

David Baneres, Robert Clariso, Josep Jorba, Montse Serra
2014 IEEE Transactions on Learning Technologies  
The technical aspects of the platform and the designed verification tool are presented.  ...  In this paper, we propose an online platform where the students can design and verify their circuits with an individual and automatic feedback.  ...  Burch, author of Logisim, for his permission to embed VerilUOC into the LogiSim GUI and distribute the resulting package.  ... 
doi:10.1109/tlt.2014.2320919 fatcat:5ldp3vfs7zbyna2m5a4t6er3hi

Fully automatic verification and error detection for parameterized iterative sequential circuits [chapter]

Tiziana Margaria
1996 Lecture Notes in Computer Science  
The paper shows how iterative parametric sequential circuits, which are most relevant in practice, can be verified fully automatically.  ...  As illustrated by means of various versions of counters, this approach captures hierarchical and mixed mode verification, as well as the treatment of varying connectivity in iterative designs.  ...  Acknowledgements The author is indebted to Michael Mendler and Claudia Gsottberger for their precious contribution in discussions and in the final realization of the case studies, and to Falk Schreiber  ... 
doi:10.1007/3-540-61042-1_49 fatcat:rjimk4w3xjeutbsrkope2k6fdm

Automatic correctness proof of the implementation of synchronous sequential circuits using an algebraic approach [chapter]

Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi
1995 Lecture Notes in Computer Science  
In this paper, we propose a technique for proving the correctness of the implementations of synchronous sequential circuits automatically, where the specifications of synchronous sequential circuits are  ...  For a given abstract level's specification, we refine the specification into a synchronous sequential circuit step by step in our framework, and prove the correctness of the refinement at each design step  ...  In this paper, we propose a technique for proving the correctness of the implementations of synchronous sequential circuits automatically, where the specifications of synchronous sequential circuits are  ... 
doi:10.1007/3-540-59047-1_48 fatcat:s7qskbvaiffjterfqcclcn4kg4

ASLAN: Synthesis of approximate sequential circuits

Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
We propose ASLAN (Automatic methodology for Sequential Logic ApproximatioN), the first effort towards the synthesis of approximate sequential circuits.  ...  In practice, however, designers are concerned with the quality of outputs generated by a sequential circuit after several cycles of computation, rather than an embedded combinational block.  ...  ASLAN: PROBLEM FORMULATION AND DESIGN APPROACH The primary objective of ASLAN is to enable automatic synthesis of approximate versions of a sequential circuit, which satisfy a designer-specified quality  ... 
doi:10.7873/date.2014.377 dblp:conf/date/RanjanRVRR14 fatcat:2tsllwi76jc6xhp6oufdtkfgou

Functional verification methodology of Chameleon processor

Françoise Casaubieilh, Geoff Barrett, Christian Berthet, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
stages of the design.  ...  -Development and use of sequential verification methods built upon a commercially available formal proof tool.  ...  Sequential proof tools can automatically prove sequential properties of complex control logic.  ... 
doi:10.1145/240518.240599 dblp:conf/dac/CasaubieilhMBBPRBEMBB96 fatcat:5tcag5cgujdo3mgqxigjqc3z64

A practical and efficient method for compare-point matching

D. Anastasakis, R. Damiano, H.-K.T. Ma, T. Stanion
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
In this paper, we describe a heuristic algorithm using ATPG for matching comparepoints based on the functionality of the combinational blocks in the sequential designs.  ...  An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified.  ...  Extension of the CPM method to handle designs with don't cares was also presented. Experimental results on large industrial circuits show the method is very efficient in practice.  ... 
doi:10.1109/dac.2002.1012640 fatcat:32lqxtxievakvnrhnufwmdje6u

A practical and efficient method for compare-point matching

Demos Anastasakis, Robert Damiano, Hi-Keung Tony Ma, Ted Stanion
2002 Proceedings - Design Automation Conference  
In this paper, we describe a heuristic algorithm using ATPG for matching comparepoints based on the functionality of the combinational blocks in the sequential designs.  ...  An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified.  ...  Extension of the CPM method to handle designs with don't cares was also presented. Experimental results on large industrial circuits show the method is very efficient in practice.  ... 
doi:10.1145/513918.513997 dblp:conf/dac/AnastasakisDMS02 fatcat:ycekfb4g45fxrg4ktfrysmxc7q

A practical and efficient method for compare-point matching

Demos Anastasakis, Robert Damiano, Hi-Keung Tony Ma, Ted Stanion
2002 Proceedings - Design Automation Conference  
In this paper, we describe a heuristic algorithm using ATPG for matching comparepoints based on the functionality of the combinational blocks in the sequential designs.  ...  An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified.  ...  Extension of the CPM method to handle designs with don't cares was also presented. Experimental results on large industrial circuits show the method is very efficient in practice.  ... 
doi:10.1145/513995.513997 fatcat:yn2fk4he4jbkfkt6bla7gawzji

A Survey of Hybrid Techniques for Functional Verification

Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
2007 IEEE Design & Test of Computers  
Sequential ATPG becomes ineffective on large, complex circuits.  ...  Researchers have also used sequential ATPG for verifying circuit properties. Its main benefit is that it requires no explicit storage of states at each time frame.  ... 
doi:10.1109/mdt.2007.30 fatcat:ojmxdheqenekzor2ybvtf7z3hi

Optimizing sequential verification by retiming transformations

Gianpiero Cabodi, Stefano Quer, Fabio Somenzi
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Sequential verification methods based on reachability analysis are still limited by the size of the BDDs involved in computations.  ...  We consider retiming as a temporary state space transformation to increase the efficiency of sequential verification.  ...  Retiming is usually applied to automatically designed circuits to target optimal clock cycle, area, or low-power, rather than minimum number of latches.  ... 
doi:10.1145/337292.337591 dblp:conf/dac/CabodiQS00 fatcat:gnkjsqpgybhvlec6f4gzoihl6u
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