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Generating VHDL Source Code from UML Models of Embedded Systems [chapter]

Tomás G. Moreira, Marco A. Wehrmeister, Carlos E. Pereira, Jean-François Pétin, Eric Levrat
<span title="">2010</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kss7mrolvja63k4rmix3iynkzi" style="color: black;">IFIP Advances in Information and Communication Technology</a> </i> &nbsp;
This work proposes an approach to generate automatically VHDL source code from UML specifications.  ...  In this context, Model-Driven Engineering approaches that use UML models are interesting options to design embedded systems, aiming at code generation of software and hardware components.  ...  Case Study This section shows an example of automatic VHDL code generation from a UML model.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-642-15234-4_13">doi:10.1007/978-3-642-15234-4_13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mj2s2plwlfd6jgvz6agmt5lnmm">fatcat:mj2s2plwlfd6jgvz6agmt5lnmm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180725021248/https://link.springer.com/content/pdf/10.1007%2F978-3-642-15234-4_13.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f2/b5/f2b51b2dc762b60d64fa060f1fc3e2b9ba36f141.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-642-15234-4_13"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS
english

Jean-Marie Gauthier, Fabrice Bouquet, Ahmed Hammad, Fabien Peureux
<span title="">2013</span> <i title="SciTePress - Science and and Technology Publications"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/lcvyca6jirfxxantcpxh4xhblq" style="color: black;">Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development</a> </i> &nbsp;
This paper proposes an approach to verify SysML models consistency and to validate the transformation of SysML models to VHDL-AMS code.  ...  The translation of SysML models into VHDL-AMS simulable code uses MMT (Model to Model Transformation) ATL Atlas Transformation Language and M2T (Model To Text) Acceleo tooling.  ...  user, i.e. system engineer, a SysML modeling guideline to generate correct VHDL-AMS code?  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5220/0004317601230128">doi:10.5220/0004317601230128</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/modelsward/GauthierBHP13.html">dblp:conf/modelsward/GauthierBHP13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/22ig24vjvrdprebprgaptombxy">fatcat:22ig24vjvrdprebprgaptombxy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922042318/https://hal.archives-ouvertes.fr/hal-00935093/document" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/13/94/1394028590be19340c0b202c8ec0e6aa07084d92.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5220/0004317601230128"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

VHDL development system and coding standard

Hans Sahm, Claus Mayer, Jörg Pleickhardt, Johannes Schuck, Stefan Späth
<span title="">1996</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 33rd annual conference on Design automation conference - DAC &#39;96</a> </i> &nbsp;
With the growing complexity of todays ASICs and the number of designers involved in one VHDL ASIC project, the need for a VHDL development system together with coding rules for simulation and synthesis  ...  This paper describes the VHDL Coding Standard which has been established and the VHDL development system including code entry, code formatting, code compliance checkers, data management and multi-user  ...  generated by the VHDL development system [7] or could be edited by any text editor.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/240518.240665">doi:10.1145/240518.240665</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/SahmMPSS96.html">dblp:conf/dac/SahmMPSS96</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fznszzbaunh7heu6cil7rs3rka">fatcat:fznszzbaunh7heu6cil7rs3rka</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810021321/http://www.cecs.uci.edu/~papers/compendium94-03/papers/1996/dac96/pdffiles/48_2.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5c/9a/5c9a26e6d7385e023ff700aeb35197049062e7dc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/240518.240665"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Formal verification of VHDL using VHDL-like ACL2 models [chapter]

Dominique Borrione, Philippe Georgelin
<span title="">2001</span> <i title="Springer US"> Electronic Chips &amp; Systems Design Languages </i> &nbsp;
We use macros to generate names, function definitions and theorems automatically, by instantiation of model skeletons, while retaining an algorithmic syntactic flavor.  ...  The recognized need for formal verification cannot be met by current automatic equivalence and model checking tools, which mainly apply to logic synthesis inputs and outputs, or require manual abstraction  ...  path from VHDL to formal proof with ACL2 System Description in Lisp System Description in VHDL VHDL compiler front-end ACL2 code generator Symbolic Simulation and Proof with ACL2 Acl2 books for VHDL  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4757-3326-6_23">doi:10.1007/978-1-4757-3326-6_23</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ndvyegcjmbftnpozdurmxljsmi">fatcat:ndvyegcjmbftnpozdurmxljsmi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20031209210726/http://www-tima-vds.imag.fr:80/Publications/Borrione-Georgelin-Lyon99.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2e/ad/2ead5920a1a5e1c95bef53278bbdaacbe7ae744b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4757-3326-6_23"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Using rapid prototyping in computer architecture design laboratories

James O. Hamblen, Henry Owen, Sudhakar Yalamanchili, Binh Dao
<span title="">1996</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/vmoxzphdj5hcvfl36qh7bj3um4" style="color: black;">Proceedings of the 1996 workshop on Computer architecture education - WCAE-2 &#39;96</a> </i> &nbsp;
In this paper, emphasis is placed upon the new core laboratories which utilize commercial CAD tools, FPGAs, hardware emulators, and a VHDL based rapid prototyping approach to simulate, synthesize, and  ...  Automatic generation of the data files to produce the prototype systems requires two to three hours of workstation time for each design.  ...  Behavioral VHDL based modeling of digital systems has been in use for several years. VHDL based logic synthesis is a newer development.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1275152.1275156">doi:10.1145/1275152.1275156</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/wcae/HamblenOYD96.html">dblp:conf/wcae/HamblenOYD96</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wyfxm6bzxbbl7b2bgbw2oh7mtu">fatcat:wyfxm6bzxbbl7b2bgbw2oh7mtu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811151613/https://projects.ncsu.edu/wcae/WCAE2/hamblen.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/3f/b9/3fb96c6ea945468c6bfcc9afe9148415055c0d92.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1275152.1275156"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A Finite State Machine modeling language and the associated tools allowing fast prototyping for FPGA devices

Bertrand Vandeportaele
<span title="">2017</span> <i title="IEEE"> 2017 IEEE International Workshop of Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM) </i> &nbsp;
Based on the ANTLR parser generator, it achieves the automatic generation of all the required .vhdl files (component, package, instantiation example and testbench) and a .dot file that is used to generate  ...  This tool also supports simple model checking and integration of additional VHDL code.  ...  This tools allows automatic inference of the interface of the model and generation of various VHDL files.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ecmsm.2017.7945900">doi:10.1109/ecmsm.2017.7945900</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zqnscda42vcw3i3ipeix6ilreq">fatcat:zqnscda42vcw3i3ipeix6ilreq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200313012548/https://hal.archives-ouvertes.fr/hal-02021357/file/ecmsm_bvandepo.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/dd/3e/dd3eec3145c9e0fd5f5d4c5d823f0b9cfe723bb2.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ecmsm.2017.7945900"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi
<span title="">1995</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC &#39;95</a> </i> &nbsp;
To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis  ...  As an experimental example, a heterogeneous system is cosimulated and prototyped successfully, which shows that our environment can be a useful heterogeneous system specification/verification environment  ...  (ii) Automatic interface model generation -Appropriate simulation models(in the form of IPC routines and VHDL models) for the interface between the two components are generated by invoking automatic interface  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224818.224848">doi:10.1145/224818.224848</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/KimKSASCS95.html">dblp:conf/aspdac/KimKSASCS95</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/w3toxz5zafbe7oywrz36m7ccx4">fatcat:w3toxz5zafbe7oywrz36m7ccx4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923045104/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1995/aspdac95/pdffiles/2c_2.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2b/63/2b635b2eeca1ccf8420b7f75c6ed9c2c9d054e7f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224818.224848"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

C/VHDL codesign for LHCb VELO zero suppression algorithms

M. Muecke
<span title="">2005</span> <i title="IEEE"> 14th IEEE-NPSS Real Time Conference, 2005. </i> &nbsp;
FPGA Design (VHDL) DSP Requirements to guarantee consistency, one of the two models has to be generated automatically.. ?  ...  synthesizable VHDL bit-and cycle-accurate C-model .vhd .c FPGA Design (VHDL) DSP (VHDL) Common code base System Simulation Framework (C++) DSP on FPGA (C) DSP.cf X Example - Linear  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/rtc.2005.1547399">doi:10.1109/rtc.2005.1547399</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gb3mkuwurvhtvmky6oie2vftwy">fatcat:gb3mkuwurvhtvmky6oie2vftwy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181030062400/http://cds.cern.ch/record/1442307/files/LHCb-TALK-2005-013.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/bd/a9/bda91c3dc9d1c0aa1d1799e39260cfe42f200991.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/rtc.2005.1547399"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Generating Simulation Models from Natural Language Specifications

W.R. Cyre, J.R. Armstrong, A.J. Honcharik
<span title="">1995</span> <i title="SAGE Publications"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/n764fe4465hw5hlo4apalbasgq" style="color: black;">Simulation (San Diego, Calif.)</a> </i> &nbsp;
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language.  ...  Both approaches are based on a modeling style in which behavior is represented by a system of interconnected processes.  ...  In all cases studied, correct VHDL code was derived automatically. In some cases, type ambiguity of a VHDL signal had to be resolved by using the post automatic link editor.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1177/003754979506500402">doi:10.1177/003754979506500402</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/q7p3sjoexbdkzizr3waaid57zy">fatcat:q7p3sjoexbdkzizr3waaid57zy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170815073152/http://www.cecs.uci.edu/~papers/compendium94-03/papers/1994/eurdac94/pdffiles/v01_1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/8e/62/8e623c413b0c8885afd9cc29a3f231bb248941c1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1177/003754979506500402"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> sagepub.com </button> </a>

Stoht

Ivanil S. Bonatti, Renato J. O. Figueiredo
<span title="">1995</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC &#39;95</a> </i> &nbsp;
A subset of this language is proposed for hardware design, including a synthesisable model for SDL's signalbased communication.  ...  An algorithm to translate this subset to fully synthesisable VHDL is proposed and implemented in a public-domain software package.  ...  approach to a hardware/software co-design methodology, b y using automatic code generation and high level synthesis.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224818.224836">doi:10.1145/224818.224836</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/BonattiF95.html">dblp:conf/aspdac/BonattiF95</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/to4xpermrvgpbkoyi2zp5e6ur4">fatcat:to4xpermrvgpbkoyi2zp5e6ur4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20040911221044/http://www.sigda.org:80/Archives/ProceedingArchives/Compendiums/papers/1995/aspdac95/pdffiles/1b_3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/92/43/92433092b2d41e1e1362623ef06dde1fca558224.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224818.224836"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Implementation of Low Density Parity Check Decoders using a New High Level Design Methodology

Syed Mahfuzul Aziz, Minh Duc Pham
<span title="2010-01-01">2010</span> <i title="International Academy Publishing (IAP)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3uo3zcmrgvgspdzqe6w6sjoezq" style="color: black;">Journal of Computers</a> </i> &nbsp;
Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems.  ...  This paper presents an efficient high level approach to designing LDPC decoders using a collection of high level modelling tools.  ...  For this purpose the VHDL code automatically generated from the Simulink models was used.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4304/jcp.5.1.81-90">doi:10.4304/jcp.5.1.81-90</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rrydty6jmndnnewizjqaku652a">fatcat:rrydty6jmndnnewizjqaku652a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20101205132437/http://ojs.academypublisher.com/index.php/jcp/article/viewFile/05018190/1348" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/fc/65/fc6503dc2c0fdf96808b76b6dee34c75b6882a1f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4304/jcp.5.1.81-90"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

System Level Tools for DSP in FPGAs [chapter]

James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer
<span title="">2001</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
In addition, the software automatically generates a faithful hardware implementation from the system model.  ...  Specific issues addressed include the mapping of system parameters into implementation (e.g., sample rates, enables), and implications of system modeling for testing (e.g., testbench generation).  ...  System Generator supports bit and cycle true modeling, and automatically generates an FPGA implementation from a system model.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-44687-7_55">doi:10.1007/3-540-44687-7_55</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/c5mygmyirvglnjawa3sin2y2xy">fatcat:c5mygmyirvglnjawa3sin2y2xy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809083039/http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_TUTORIALS_dr/SysGen_dr/VPR89D6KX8A3HWFC.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/eb/6d/eb6d61da7618679814390859a86244778c53614f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-44687-7_55"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems

Yu Jiang, Hehua Zhang, Huafeng Zhang, Xinyan Zhao, Han Liu, Chengnian Sun, Xiaoyu Song, Ming Gu, Jiaguang Sun
<span title="">2014</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dj7g645z6zfl5lut4iwy5walyu" style="color: black;">Proceedings of the 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering - FSE 2014</a> </i> &nbsp;
and debug the system model, (3) a verification engine to verify the correctness of the system design, and (4) a synthesis engine to automatically generate efficient executable VHDL code from the model  ...  in a single framework, (2) how to ensure the correctness of the model, and (3) how to maintain the consistency between the model and the implementation of the system.  ...  This component automatically generates efficient VHDL code from the graphical model, which can be directly loaded into FPGA processor for execution.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2635868.2661664">doi:10.1145/2635868.2661664</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/sigsoft/JiangZZZLSSGS14.html">dblp:conf/sigsoft/JiangZZZLSSGS14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/k243chgzzjcgtde3cqjlvz275a">fatcat:k243chgzzjcgtde3cqjlvz275a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20160928165447/http://chengniansun.bitbucket.org:80/papers/fse14-tool.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c1/6d/c16da8c9036c0d66ec287aef463468bba200ac71.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2635868.2661664"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Soft IP Customisation Model Based on Metaprogramming Techniques

Vytautas Štuikys, Robertas Damaševičius
<span title="2004-01-01">2004</span> <i title="Vilnius University Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2euqyspe25eahoco4ofscpbnai" style="color: black;">Informatica</a> </i> &nbsp;
We propose a layered Soft IP Customisation (SIPC) model for specifying and implementing system-level soft IP design processes such as wrapping and customisation.  ...  the metaprogramming techniques, and (3) Generation Layer for generation of the customised soft IP instances from metaspecifications.  ...  The generation process is performed automatically using a metalanguage processor.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.15388/informatica.2004.049">doi:10.15388/informatica.2004.049</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/buzu3xgclfdrhkcz76nhx4qici">fatcat:buzu3xgclfdrhkcz76nhx4qici</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809100043/https://www.mii.lt/informatica/pdf/info541.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/57/af/57af9afc2dc026e347ed4e44eb7272733f75ef0f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.15388/informatica.2004.049"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

V-HOLT verifier - An automatic formal verification tool for combinational circuits

Nirmal Saeed, Ayesha Inam, Aisha Khan, Osman Hasan
<span title="">2012</span> <i title="IEEE"> 2012 15th International Multitopic Conference (INMIC) </i> &nbsp;
The translation to HOL4 compatible code and the generation of HOL4 verification script is automatically done and thus the user is not involved with these details, which makes V-HOLT Verifier quite user  ...  As a first step to overcome these limitations, we present an automatic verification tool, V-HOLT Verifier, for the verification of combinational circuits described in VHDL format.  ...  For this purpose, we developed an automatic test-bench generator (Translator T1) to save the user the trouble of having to generate a test-bench for any given VHDL code.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/inmic.2012.6511465">doi:10.1109/inmic.2012.6511465</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/d4ydoqxsyfaozo5423hhhwgowu">fatcat:d4ydoqxsyfaozo5423hhhwgowu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20171208190452/http://save.seecs.nust.edu.pk:80/pubs/INMIC12.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ff/0d/ff0dd1af2edf8a95d6d56290bb63164ab27e170c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/inmic.2012.6511465"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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