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Automatic Synthesis of SystemC-Code from Formal Specifications [chapter]

Carsten Rust, Achim Rettberg
IFIP International Federation for Information Processing  
We describe a method for synthesizing SystemC-Code from high-level Petri nets.  ...  The methodology leads through the complete design process from modelling on an abstract level using high-level Petri nets via analysis and partitioning of the model down to automatic synthesis of an implementation  ...  Automatic Synthesis of SystemC-Code from Formal Specifications 189 blockdiagrams for representing the entire system (e.g. [8]).  ... 
doi:10.1007/1-4020-8149-9_19 dblp:conf/ifip10-3/RustR04 fatcat:d65tpwxyqvc5hng7a4fkfvypyy

The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems

A. Herrholz, F. Oppenheimer, P. A. Hartmann, A. Schallenberg, W. Nebel, C. Grimm, M. Damm, J. Haase, F. Brame, F. Herrera, E. Villar, I. Sander (+3 others)
2007 2007 International Conference on Field Programmable Logic and Applications  
The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.  ...  The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC.  ...  Finally the refined SystemC system model is the entry point for automatic synthesis.  ... 
doi:10.1109/fpl.2007.4380679 dblp:conf/fpl/HerrholzOHSNGDHBHVSJFM07 fatcat:uhneslblq5etlkorfljeiefxcu

SystemCoDesigner

Christian Haubelt, Thomas Schlichter, Joachim Keinert, Mike Meredith
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Starting from a behavioral SystemC model, hardware accelerators can be generated automatically using Forte Cynthesizer and can be added to the design space.  ...  The resulting design space is explored automatically by optimizing several objectives simultaneously using state of the art multi-objective optimization algorithms.  ...  Moreover, tools for automatic code generation for embedded processors exist [15, 20] . However, efficient synthesis approaches from ESL models to hardware/software implementations are still missing.  ... 
doi:10.1145/1391469.1391616 dblp:conf/dac/HaubeltSKM08 fatcat:p7cn7wnmkfchrma2477dvmoski

Possibility of SystemC code generation from SDL specification

Pavel Morozkin
2012 2012 11th Conference of Open Innovations Association (FRUCT)  
finally by generating of SystemC code from this tree.  ...  In particular, the use of SDL language for design of formal specification of communication systems has more than thirty years story.  ...  Automatic SystemC code generation from SDL specification is one of the most interesting and efficient solution. B.  ... 
doi:10.23919/fruct.2012.8253112 dblp:conf/fruct/Morozkin12a fatcat:n3e5vozy5bd7vagq3dl6fodb7i

Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study

Ghislain Roquier, Matthieu Wipliez, Mickael Raulet, Jorn W. Janneck, Ian D. Miller, David B. Parlour
2008 2008 IEEE Workshop on Signal Processing Systems  
This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model.  ...  In this framework, a decoder is built as a configuration of video coding modules taken from the standard "MPEG toolbox library".  ...  The interest of having an automatic C software synthesis is two-folded.  ... 
doi:10.1109/sips.2008.4671776 dblp:conf/sips/RoquierWRJMP08 fatcat:r3eabufhavgzpasvetr3ixolgm

Specification of adaptive HW/SW systems in SystemC

Fernando Herrera, Eugenio Villar, Philipp A. Hartmanny
2008 2008 Forum on Specification, Verification and Design Languages  
This paper proposes a SystemC-based specification methodology of adaptive embedded systems to be implemented on a platform including one or more processors, thus supporting the execution of embedded software  ...  For it, it proposes the collaboration of two specification methodologies: HetSC and OSSS+R. The main issues for the integration of these specification methodologies are addressed.  ...  The OO SystemC specification feeds a synthesis tool called OOAS, which generates synthesizeable SystemC code.  ... 
doi:10.1109/fdl.2008.4641422 dblp:conf/fdl/HerreraVH08 fatcat:tdnqa64fqvec5ivdxfrlyd5abu

A UML-based approach for heterogeneous IP integration

Sun Zhenxin, Wong Weng-Fai
2009 2009 Asia and South Pacific Design Automation Conference  
We built a code generator to produce the interface adapters from the UML models. We experimented with our approach using simple-bus and a MPEG-2 decoder as case studies.  ...  In this paper, we propose an interface synthesis method that uses the UML notation to model the interfaces of predefined components and glue logic within the standard OCPcompliant environment.  ...  We will synthesis both types of the connection from their descriptions specified in wrapper classes. III User Input Many specification formalisms today use graphical notations.  ... 
doi:10.1109/aspdac.2009.4796473 dblp:conf/aspdac/SunW09 fatcat:rd5idr7pyvek7mnamwfddpsb74

An Introduction to High-Level Synthesis

P. Coussy, D.D. Gajski, M. Meredith, A. Takach
2009 IEEE Design & Test of Computers  
High-Level Synthesis The synthesis tasks can be performed manually or automatically.  ...  Another advantage of an untimed source is that it avoids errors resulting from manual coding of architectural details.  ... 
doi:10.1109/mdt.2009.69 fatcat:5wa4gs37krgzziwtiftffzszqe

Introduction to high-level synthesis

D.D. Gajski, L. Ramachandran
1994 IEEE Design & Test of Computers  
High-Level Synthesis The synthesis tasks can be performed manually or automatically.  ...  Another advantage of an untimed source is that it avoids errors resulting from manual coding of architectural details.  ... 
doi:10.1109/54.329454 fatcat:xob6dmmhjngvfh7d6f7jpv35ly

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006 2006 IEEE International SOC Conference  
The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing  ...  The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC.  ...  ACKNOWLEDGMENTS This research is partially supported by the Semiconductor Research Corporation, the Gigascale Silicon Research Center, the National Science Foundation, and grants from Altera Corporation  ... 
doi:10.1109/socc.2006.283880 dblp:conf/socc/CongFHJZ06 fatcat:yupmpajpw5ec7lertm6uqxy2ne

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)

Fateh Boutekkouk, Mohammed Benmohammed, Sebastien Bilavarn, Michel Auguin
2009 Journal of Object Technology  
), which is one of the basic principles of DIPLODOCUS conflicts or not with formal semantics of LOTOS.  ...  The main limitations are : Since the same abstract specification serves as input to both formal analysis and abstract simulation, It is not clear whether abstraction (in both data and tasks internal behaviour  ...  This profile intends to describe System-On-Chip specific information using UML. It integrates concepts from SOCs and allows automatic code generation for hardware (eg.  ... 
doi:10.5381/jot.2009.8.1.a1 fatcat:coirvylxd5amzmiwtz6ymxi6l4

A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications

R. Siegmund, D. Muller
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
The formalism used for protocol specification and a corresponding hardware synthesis algorithm from such specifications are presented.  ...  In our approach, controller hardware in form of RTL models is synthesized from a formal specification of a communication protocol.  ...  The methodology is based on synthesis of controller hardware from a formal high-level specification of the protocol.  ... 
doi:10.1109/dac.2002.1012696 fatcat:wimime3brvc2nah7voc2cnjmdy

A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications

Robert Siegmund, Dietmar Müller
2002 Proceedings - Design Automation Conference  
The formalism used for protocol specification and a corresponding hardware synthesis algorithm from such specifications are presented.  ...  In our approach, controller hardware in form of RTL models is synthesized from a formal specification of a communication protocol.  ...  The methodology is based on synthesis of controller hardware from a formal high-level specification of the protocol.  ... 
doi:10.1145/514069.514071 fatcat:uotuby67c5ezpfqk6l6pxm2vji

A SysML and CLEAN-based methodology for digital circuits design

Zakaria Lakhdara, Salah Merniz
2016 International Journal of High Performance Systems Architecture  
To this aim, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modeling hardware designs.  ...  A case study involving the functional implementation of an ALU (Arithmetic Logic Unit) through Clean code generated from high level SysML diagrams is given, to practically show the potential features of  ...  The automatic code generation from an electronic schema and the reuse of the saved specifications in the library minimize the circuit design time.  ... 
doi:10.1504/ijhpsa.2016.10002660 fatcat:4la3zutmhrhrnc2g6uct2o2zby

A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications

Robert Siegmund, Dietmar Müller
2002 Proceedings - Design Automation Conference  
The formalism used for protocol specification and a corresponding hardware synthesis algorithm from such specifications are presented.  ...  In our approach, controller hardware in form of RTL models is synthesized from a formal specification of a communication protocol.  ...  The methodology is based on synthesis of controller hardware from a formal high-level specification of the protocol.  ... 
doi:10.1145/513918.514071 dblp:conf/dac/SiegmundM02 fatcat:wnodhllnujeuffm3kpjzln5uou
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