Filters








47,058 Hits in 7.8 sec

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, DanielD Gajski
2008 EURASIP Journal on Embedded Systems  
The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation.  ...  In addition to this pin-accurate model (PAM), our communication refinement also generates a fast-simulating TLM of the system, which abstracts away the pin-level details of individual bus transactions  ...  Supporting architecture exploration and automated refinement via intermediate design models, OSSS feeds into the FOSSY synthesis tool for implementation in hardware and software.  ... 
doi:10.1155/2008/647953 fatcat:peu5knjzivdjjmaarphxga6nc4

A mapping framework for guided design space exploration of heterogeneous MP-SoCs

Bastian Ristau, Torsten Limberg, Gerhard Fettweis
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
We will show how the behavior of such systems can be analyzed without the need for time-consuming implementations of simulation models.  ...  This enables fast evaluation and modification of a given system at a very early design stage allowing efficient pruning of the design space.  ...  In this paper we present a framework for automatic temporal and spatial mapping based on abstract models of algo-rithms and architecture.  ... 
doi:10.1145/1403375.1403564 fatcat:h62ecdepd5gmdljdqwwrcpss2e

Specify-explore-refine (SER)

A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Following a Specify-Explore-Refine methodology, SER supports system-level design space exploration, interactive platform development and automatic model refinement and model generation.  ...  With SER at its core, ELEGANT provides a seamless tool chain for modeling verification and synthesis from top-level specification down to embedded HW/SW implementation.  ...  As a result of network exploration, SER inserts transducers, merges and refines channels from the architecture model and generates and exports the refined network model implementing the upper communication  ... 
doi:10.1145/1391469.1391617 dblp:conf/dac/GerstlauerPSGNAN08 fatcat:pqfqi4vk5zcijgeaukomditlxy

System-level memory modeling for bus-based memory architecture exploration

Zhongbo Cao, Ramon Mercado, Diane T. Rover
2009 2009 IEEE International Conference on Electro/Information Technology  
In particular, we extend the SpecC methodology by defining various memory models at different levels of abstraction and a set of refinement rules that support fast and accurate memory architecture exploration  ...  Computation Architecture Model Abstract Memory Architecture Model Memory Architecture Exploration Detailed Memory Architecture Model Memory Architecture Refinement Implementation Model RTL Synthesis Specification  ...  MEMORY MODELING AND REFINEMENTS Newly defined memory models provide a system level solution for fast and efficient memory design space exploration.  ... 
doi:10.1109/eit.2009.5189619 dblp:conf/eit/CaoMR09 fatcat:bzm4r2gfofacvatcq6gacgwj4a

Software Performance Estimation in MPSoC Design

Marcio Oyamada, Flavio R. Wagner, Marius Bonaciu, Wander Cesario, Ahmed Jerraya
2007 2007 Asia and South Pacific Design Automation Conference  
From this architectural definition, a tool that refines hardware and software interfaces produces a bus-functional model.  ...  Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration.  ...  The simulation model for system evaluation is automatically generated from the architecture description in the MaxSim environment.  ... 
doi:10.1109/aspdac.2007.357789 dblp:conf/aspdac/OyamadaWBCJ07 fatcat:hbz34b4l7jampnvlvq6c2wsj6q

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jurgen Teich
2010 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design.  ...  implementation-level models starting from a formal application model and generic MPSoC architecture templates.  ...  All in all, results demonstrate the feasibility and benefits of fast and expressive formal streaming application models for high-level algorithmic design coupled with automatic synthesis for rapid exploration  ... 
doi:10.1109/icsamos.2010.5642076 dblp:conf/samos/GladigauGHST10 fatcat:pjs6j3fybzhlpgx3jtl3wqskwi

Electronic System-Level Synthesis Methodologies

A. Gerstlauer, C. Haubelt, A.D. Pimentel, T.P. Stefanov, D.D. Gajski, J. Teich
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
from specification to implementation for complete systems across hardware and software boundaries.  ...  In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context.  ...  For SCE, we would like to acknowledge the main developers, namely Rainer Dömer, Junyu Peng, Dongwan Shin and Quoc-Viet Dang.  ... 
doi:10.1109/tcad.2009.2026356 fatcat:vkvmjvxvvrbx5n3xnvbrjaerl4

A SW performance estimation framework for early system-level-design using fine-grained instrumentation

T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers, H. Meyr
2006 Proceedings of the Design Automation & Test in Europe Conference  
Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity  ...  Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative.  ...  In the field of simulation based SoC architecture analysis, the ARTEMIS [7] project is focused on automatic refinement of Kahn Process Network algorithm models to archi-tecture models for the purpose  ... 
doi:10.1109/date.2006.243830 dblp:conf/date/KempfKWALM06 fatcat:nhoemvoktrh3dgmhzumc2v4vne

System-level communication modeling for network-on-chip synthesis

Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
In this paper, we define system communication abstraction layers and corresponding design models that support successive, stepwise refinement from abstract message-passing down to a cycleaccurate, bus-functional  ...  The key to the SUCC~SS of any design flow are well-defined abstraction levels and models, which enable automation of early vaIidalion, synthesis and verification.  ...  Table I1 summarizes the results for the example design. Using the refinement tools, models of the example design were automatically generated within seconds.  ... 
doi:10.1145/1120725.1120740 dblp:conf/aspdac/GerstlauerSDG05 fatcat:rqluk5ea3vd3tiqv3ratuvbjsa

Creating Explicit Communication in SoC Models Using Interactive Re-Coding

Pramod Chandraiah, Junyu Peng, Rainer Domer
2007 2007 Asia and South Pacific Design Automation Conference  
Researchers in the CAD community have proposed fast and efficient techniques for comprehensive design space exploration to expedite this critical design step.  ...  In this paper, we propose an efficient interactive approach to explicit communication creation by automating some of the common coding tasks in specification models for communication exploration.  ...  In this paper, we only focus on the refinement steps that were necessary to generate the Architectural Model for communication exploration.  ... 
doi:10.1109/aspdac.2007.357791 dblp:conf/aspdac/ChandraiahPD07 fatcat:vp6ryiyjazf6zbyw7m4v4f3vma

Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL

M. Anouar Dziri, Firaz Samet, Flavio Rech Wagner, Wander O. Cesário, Ahmed A. Jerraya
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
A new approach to obtain a full path to implementation for SoC design is proposed.  ...  Abstract architecture Architecture Exploration : HW/SW partitioning + performance test Architecture Design : Components design + HW/SW interfaces design VCC ROSES Macro architecture RTL architecture Link  ...  automatically generate a virtual architecture structure in order to launch the automatic refinement process.  ... 
doi:10.1145/1119772.1119816 dblp:conf/aspdac/DziriSWCJ03 fatcat:xppjfcsgdfhrdcetscztk2wmra

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Domer, Daniel D. Gajski
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures.  ...  In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures.  ...  Given designer decisions, our tools automatically refine a virtual architecture model of the system down to TLM and PAM implementations.  ... 
doi:10.1109/tcad.2007.895794 fatcat:cqrbgqnhurfzremouexfn5jwmu

Transaction level modeling

Lukai Cai, Daniel Gajski
2003 Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis - CODES+ISSS '03  
However, the transaction-level models(TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated  ...  Recently, the transaction-level modeling has been widely referred to in system-level design community.  ...  An example of meetin-the-middle approach is VCC [5] for architecture estimation/exploration and N2C [1] for interface synthesis.  ... 
doi:10.1145/944650.944651 fatcat:rnvmfc4fuzhcvmelqnogjs22ti

Transaction level modeling

Lukai Cai, Daniel Gajski
2003 Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis - CODES+ISSS '03  
However, the transaction-level models(TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated  ...  Recently, the transaction-level modeling has been widely referred to in system-level design community.  ...  An example of meetin-the-middle approach is VCC [5] for architecture estimation/exploration and N2C [1] for interface synthesis.  ... 
doi:10.1145/944645.944651 dblp:conf/codes/CaiG03 fatcat:fqpldyiaxne4tl4vu5rk4qu25y

Framework For Efficient Cosimulation And Fast Prototyping On Multi-Components With Aaa Methodology: Lar Codec Study Case

Erwan Flécher, Mickael Raulet, Ghislain Roquier, Marie Babel, O. Deforges
2007 Zenodo  
Next, language and architecture models are gradually refined and the system is cosimulated for early validation.  ...  It is a matrix-based language including high-level functions for fast application modeling.  ... 
doi:10.5281/zenodo.40543 fatcat:rf3kwvaherfv5mckeubyqojiru
« Previous Showing results 1 — 15 out of 47,058 results