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Automatic Generation of Custom Parallel Processors for Morphological Image Processing

Emerson Carlos Pedrino, Marcio Merino Fernandes
2014 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing  
Acknowledgments  The authors would like to thank the Brazilian agencies FAPESP (grant no. 12/13899-9), and CNPq (grant no. 478084/2012-9), for their financial support.  ...  : Example of an output from the prototype tool Automatic Generation: Reconfiguration Process  The reconfiguration of the parallel architecture is made during the FPGA programming process  ...  In all cases, the final result was identical for both.  Morphological Image Processing: a nonlinear branch in Image Processing and very important in industrial applications.  ... 
doi:10.1109/sbac-pad.2014.47 dblp:conf/sbac-pad/PedrinoF14 fatcat:qwhydqoqqvfr7ejgzdlg2mcqge

Rapid prototyping of an automated video surveillance system: a hardware-software co-design approach

Hau T. Ngo, Ryan N. Rakvic, Randy P. Broussard, Robert W. Ives, Sos S. Agaian, Sabah A. Jassim, Yingzi Du
2011 Mobile Multimedia/Image Processing, Security, and Applications 2011  
Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon Streaming video protocol.  ...  Time-critical steps of the video surveillance algorithm are designed and implemented in the FPGA's logic elements to maximize parallel processing.  ...  Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon-ST video protocol.  ... 
doi:10.1117/12.884331 fatcat:eroolpvgqbhglnbvuvnltugfvm

Automatic license plate recognition on microprocessors and custom computing platforms: A review

Princewill Akpojotor, Adebayo Adetunmbi, Boniface Alese, Ayodeji Oluwatope
2021 IET Image Processing  
Custom platforms for ALPR consume less power and achieve high processing speed for real-time capability.  ...  Automatic license plate recognition (ALPR) is the process of extracting and recognizing character information within a localized license plate region.  ...  ACKNOWLEDGEMENTS The authors would like to thank Science and Technology Education at the Post-Basic Level (STEP-B) for providing access to materials, through a World Bank grant for the establishment of  ... 
doi:10.1049/ipr2.12262 fatcat:wvlkalpj2na25aletvg377ww24

Advanced image processing package for FPGA-based re-programmable miniature electronics

Vladimir I. Ovod, Christopher R. Baxter, Mark A. Massie, Paul L. McCarley, Bjorn F. Andresen, Gabor F. Fulop
2005 Infrared Technology and Applications XXXI  
Flexible FPGA designs of these operations and re-programmability of the processing board allows for easy updates of the VASI™ sensors, and for low-cost customization of VASI™ sensors taking into account  ...  This paper describes the image processing algorithms implemented and verified in Xilinx FPGAs and provides the major technical performances with figures illustrating practical applications of the processing  ...  Flexible FPGA designs of these techniques and re-programmability of the processing board allows for low-cost and quick turn-around of customized applications of VASI™ and other state of the art imaging  ... 
doi:10.1117/12.603019 fatcat:b22zdf6y7ndgnd7vopyxkfqw2e

Computer vision algorithms on reconfigurable logic arrays

N.K. Ratha, A.K. Jain
1999 IEEE Transactions on Parallel and Distributed Systems  
Ratha Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For  ...  General-purpose parallel processors Many general-purpose parallel processing systems are being used for computer vision tasks.  ...  A generalized 2 - 2 D convolution is of signi cant importance for low-level vision tasks.Most of the image processing accelerators support template matching and morphological processing as independent  ... 
doi:10.1109/71.744833 fatcat:htpcqypklnghvfdedyl7dneyhu

Tools for code optimization and system evaluation of the image processing system PAPRICA-3

Massimo Bertozzi, Alberto Broggi
1999 Journal of systems architecture  
The whole environment has been used to validate possible solutions for the hardware system and to develop, test, and tune several real-time image processing applications.  ...  Applications are developed in C++ using high level data types and the corresponding Assembly code is automatically created by a code generator.  ...  Acknowledgements This work was partially supported by the Italian CNR under the frame of the Progetto Finalizzato Trasporti 2.  ... 
doi:10.1016/s1383-7621(98)00021-6 fatcat:bri52ke55vdofd76zqrqb5wjje

Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler [chapter]

Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
2016 Lecture Notes in Computer Science  
To unlock this limitation, this paper presents an automatic parallelization technique for auto-generated C code developed by MATLAB/Simulink with Embedded Coder.  ...  Also, this paper proposes an automatic profiling framework for the auto-generated code for enhancing static scheduling, which leads to improving the performance of MATLAB/Simulink applications.  ...  ., LTD. for providing the anomaly detection model. We would like to express appreciation to A&D CO., LTD..  ... 
doi:10.1007/978-3-319-29778-1_8 fatcat:2jhp6m2iqrfrhardeqkddqwicm

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

Alberto Broggi, Massimo Bertozzi, Alessandra Fascioli
2000 Real-time imaging  
T his paper discusses the main architectural issues of a challenging application of real-time image processing: the vision-based automatic guidance of road vehicles.  ...  engines Ð a massively parallel special-purpose SIMD architecture and a general-purpose system Ð while future trends in this ®eld are proposed, based on the experience of the ARGO project.  ...  Acknowledgement This work has been partially supported by the Italian National Research Council (CNR) in the framework of the MADESS2 Project; up to date information can be found at  ... 
doi:10.1006/rtim.1999.0191 fatcat:462ifiev6ffmbl5m55sqhgwu5u

Towards a Heterogeneous Medical Image Registration Acceleration Platform

William Plishker, Omkar Dandekar, Shuvra Bhattacharyya, Raj Shekhar
2007 2007 IEEE Biomedical Circuits and Systems Conference  
Accurate image registration enhances diagnoses of patients, accounts for changes in morphology of structures over time, and even combines images from different modalities.  ...  (e.g. multiprocessors, graphics processors, field programmable gate arrays) match these types of parallelism.  ...  We would like to express our thanks for the assistance of the UMIACS staff, the Imaging Technologies Laboratory, and the DSPCAD group.  ... 
doi:10.1109/biocas.2007.4463351 fatcat:byfcm7th7rh2hlkm2lfzkps6ji

Towards the Optimal Hardware Architecture for Computer Vision [chapter]

Alejandro Nieto, David Lpez, Vctor Brea
2012 Machine Vision - Applications and Systems  
When using in low-level image processing, fine-grain processor arrays match with massively parallel operations such as filters or morphological operations.  ...  For instance, SCAMP processor (Dudek & Hicks, 2005) exploits the massively spatial parallelism of low-level operations, integrating processing units and sensors in a processor-per-pixel fashion.  ... 
doi:10.5772/34023 fatcat:higcvn5ffrhzlieberxwiatasa

High performance motion detection: some trends toward new embedded architectures for vision systems

Lionel Lacassagne, Antoine Manzanera, Julien Denoulet, Alain Mérigot
2008 Journal of Real-Time Image Processing  
We present some implementations of robust motion detection algorithms on three architectures: a general purpose RISC processor-the PowerPC G4-a parallel artificial retina dedicated to low level image processing-Pvlsar34  ...  an estimation of what should be the components of a next generation vision system.  ...  Acknowledgment We wish to thanks Joel Falcou for his valuable help.  ... 
doi:10.1007/s11554-008-0096-7 fatcat:xzdxst3wrjfz3nglhk4tmbfzxe

Practical Parallel Rendering of Detailed Neuron Simulations [article]

Juan B. Hernando, John Biddiscombe, Bidur Bohara, Stefan Eilemann, Felix Schürmann
2013 Eurographics Symposium on Parallel Graphics and Visualization  
Parallel rendering of large polygonal models with transparency is challenging due to the need for alpha-correct blending and compositing, which is costly for very large models with high depth complexity  ...  We present the optimized algorithms needed to achieve interactive frame rates for a non-trivial, real-world parallel rendering scenario.  ...  Acknowledgments This work was supported in part by the Blue Brain Project, the Swiss National Science Foundation under Grant 200021-116329/1 and by the Spanish Ministry of Science and Innovation under  ... 
doi:10.2312/egpgv/egpgv13/049-056 fatcat:gbqnbmg42bchlhzqt33a25mzii

On fast development of FPGA-based SOA services—machine vision case study

A. Ruta, R. Brzoza-Woch, K. Zielinski
2012 Design automation for embedded systems  
The platform has been tuned to act as a flexible runtime environment for image processing services, thus providing functionality of an intelligent camera.  ...  Despite the automation of this process with numerous EDA tools available, no well-established design patterns exist.  ...  The previously generated accelerator is automatically recognized as a custom IP core.  ... 
doi:10.1007/s10617-012-9084-z fatcat:rochnoeayzgbppl3igquletz6u

High-speed image processing algorithms using MMX hardware

John W. V. Miller, James Wood, Susan S. Solomon, Bruce G. Batchelor, John W. V. Miller
1997 Machine Vision Applications, Architectures, and Systems Integration VI  
Benchmarks for a number of image-processing operations are provided in the paper to illustrate the advantages of the new multimedia extensions for vision applications.  ...  Special instructions are provided with this type of hardware which, combined with a SIMD parallel processing architecture, provides a substantial speed improvement over more traditional processors.  ...  the University of Michigan-Dearborn.  ... 
doi:10.1117/12.285568 fatcat:sojgs7nkgbclrhzqoecdkru5k4

Performance analysis of massively parallel embedded hardware architectures for retinal image processing

Alejandro Nieto, Victor Brea, David L Vilariño, Roberto R Osorio
2011 EURASIP Journal on Image and Video Processing  
Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing.  ...  In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays  ...  Authors would also like to thank the reviewers for their helpful comments and suggestions.  ... 
doi:10.1186/1687-5281-2011-10 fatcat:btr34shqvbbmzp7khw5k64qwki
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