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Automatic Formal Synthesis of Hardware from Higher Order Logic

Mike Gordon, Juliano Iyoda, Scott Owens, Konrad Slind
2006 Electronical Notes in Theoretical Computer Science  
Introduction Our goal is to synthesise correct-by-construction hardware directly from mathematical specifications in higher order logic (HOL [5]).  ...  A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described.  ...  Acknowledgements David Greaves gave us advice on the hardware implementation of handshake protocols and also helped us understand the results of simulating circuits produced by our compiler.  ... 
doi:10.1016/j.entcs.2005.10.003 fatcat:cmw4t4ctmze7dipfzvjtb2z4le

Proof producing synthesis of arithmetic and cryptographic hardware

Konrad Slind, Scott Owens, Juliano Iyoda, Mike Gordon
2007 Formal Aspects of Computing  
We have implemented a novel compiler from a 'synthesisable subset' of higher order logic to clocked synchronous hardware.  ...  The synthesisable subset of higher order logic can be extended.  ...  We have implemented a novel compiler from a 'synthesisable subset' of higher order logic to clocked synchronous hardware.  ... 
doi:10.1007/s00165-007-0028-5 fatcat:gquwxs6cjze73okg5ztvj2775i

Formal synthesis in circuit design — A classification and survey [chapter]

Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
1996 Lecture Notes in Computer Science  
We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view.  ...  We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation.  ...  Acknowledgements The authors are grateful to the anonymous referees whose constructive comments have improved the quality of the paper.  ... 
doi:10.1007/bfb0031817 fatcat:bz6cob6jd5bo3izawypciavotq

Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System [chapter]

Matthias Mutz
1997 IFIP Advances in Information and Communication Technology  
The higher order logic theorem proving system HOL is used to define formal hardware models, to define an implementation relation between these models, and to develop the verification procedure.  ...  The paper discusses the development of automatic post-synthesis verification support for a high level synthesis step.  ...  Such formal synthesis approaches often use systems based on higher order logic, e.g.  ... 
doi:10.1007/978-0-387-35190-2_19 fatcat:veqbp6f5ojbclmbygzctrpmqbm

Intelligent Custom Block Generation

Michael F. Dossis
2014 Universal Journal of Electrical and Electronic Engineering  
The contribution of this work is a formal and intelligent HLS synthesis and rapid verification methodology with custom options, which re-uses and incorporates the generation of predesigned custom hardware  ...  The usability of the proposed methodology is confirmed with a number of HLS benchmarks including a hierarchical RSA crypto-processor design and a line-drawing algorithm from computer graphics.  ...  Acknowledgements This work was partially supported by the TEI of Western Macedonia, Greece.  ... 
doi:10.13189/ujeee.2014.020203 fatcat:73z4hwmfqrha3k6bkhogtjzzwu

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Michael Dossis
2013 Advances in Robotics & Automation  
Citation: Dossis M (2014) Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques. Adv Robot Autom 3: 121.  ...  A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler  ...  The synthesis transformations are enhanced with XML schema validation as well as RDF logic relations to implement the execution and formal validation of the prototype hardware compiler.  ... 
doi:10.4172/2168-9695.1000121 fatcat:6vwlruh4yfg2bi6dhyhmz2uoy4

Formal verification of hardware correctness: introduction and survey of current research

P. Camurati, P. Prinetto
1988 Computer  
His formal system based on higher-order predicates is called HOL, but the same name is given to the automatic theorem-prover.  ...  The authors used this approach for automatic synthesis of state diagrams starting from temporal logic specifications. thesystem'sefficiency, including filtering of descristions.  ...  Camurati's interests include CAD for VLSI, including hardware description languages, design for testability, testing and ATPG, and formal verification; and application of AI techniques to CAD, CAT, and  ... 
doi:10.1109/2.65 fatcat:dn5xh3m4gbacfffc5ogxybxbjm

High-level Synthesis [article]

Issam Damaj
2019 arXiv   pre-print
Hardware synthesis is a general term used to refer to the processes involved in automatically generating a hardware design from its specification.  ...  The chained synthesis tasks at each level of the design process include system synthesis, register-transfer synthesis, logic synthesis, and circuit synthesis.  ...  Towards Automated Hardware Design Translation from higher levels of abstraction for software has motivated the creation of automated hardware design (synthesis) tools.  ... 
arXiv:1905.02076v1 fatcat:ffzc23yqevauji7hc42lazlila

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

K. Wakabayashi, T. Okamoto
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators.  ...  The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system.  ...  Yoshimura for his contribution in developing a prototype of the algorithm and system for our floorplanner.  ... 
doi:10.1109/43.898829 fatcat:qxt6wpnijbc7bccbfqtphac4ua

A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality

Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita
2020 IPSJ Transactions on System LSI Design Methodology  
In order to remove as many redundancies as possible, instead of removing the redundant single faults first, we clear up the redundant faults from higher cardinality to lower cardinality.  ...  In this paper, we propose a logic optimization method to remove the redundancy in the circuit. The incremental Automatic Test Pattern Generation method is used to find the redundant multiple faults.  ...  In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques.  ... 
doi:10.2197/ipsjtsldm.13.35 fatcat:vft27es3zra4xldze7g7jdysli

Design space exploration for automatically generated cryptographic hardware using functional languages

Davy Wolfs, Kris Aerts, Nele Mentens
2012 22nd International Conference on Field Programmable Logic and Applications (FPL)  
The novelty in our approach lies in the fact that we exploit the higher-order features of functional languages to facilitate the design space exploration and that we take benefit from the strength of the  ...  third-party synthesis tool by generating VHDL code at an abstraction level that is higher than the gate level.  ...  We also shift from basic logic gates to formal FSMs for the description of the control path, as is common in VHDL programming.  ... 
doi:10.1109/fpl.2012.6339174 dblp:conf/fpl/WolfsAM12 fatcat:nmpki6cor5etzmjbvn6pyqwtjy

Detecting Malicious Logic Through Structural Checking

Scott C. Smith, Jia Di
2007 2007 IEEE Region 5 Technical Conference  
Hardware is just as susceptible as software to "hacker attacks", through inclusion of malicious logic; and the consequences of such an attack could be disastrous!  ...  However, the nature of malicious logic and defending against it is fundamentally different from its software counterpart.  ...  More expressive logics, such as higher order and modal logics, allow for convenient expression of a wider range of problems than first order logic, but theorem proving for these logics is less developed  ... 
doi:10.1109/tpsd.2007.4380384 fatcat:heizx3n5fbgdhb3sfbqzvoekjm

Design-Flow and Synthesis for ASICs: A Case Study

Massimo Bombana
1995 Proceedings - Design Automation Conference  
In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices.  ...  The problem of relating the different abstraction levels involved in the extended design process is solved through the use of logic synthesis tools.  ...  ÊÊÊÊ LAMBDA4.2 formal synthesis Formal library aligned ËËËË Transformational ËËËË ËËËË Module VHDL Database logic vhdl mixed simulation synthesis Logic synthesis Circuit Data Base AREA TIMING analysis  ... 
doi:10.1109/dac.1995.249962 fatcat:5ulddl4rrraqpgz5wleeb5o6du

Design-flow and synthesis for ASICs

Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices.  ...  The problem of relating the different abstraction levels involved in the extended design process is solved through the use of logic synthesis tools.  ...  ÊÊÊÊ LAMBDA4.2 formal synthesis Formal library aligned ËËËË Transformational ËËËË ËËËË Module VHDL Database logic vhdl mixed simulation synthesis Logic synthesis Circuit Data Base AREA TIMING analysis  ... 
doi:10.1145/217474.217544 dblp:conf/dac/BombanaCCHMZ95 fatcat:iovpvob7d5hvpczrikhgaatmna

Assertion checkers - enablers of quality design

Marc Boule, Zeljko Zilic
2008 2008 1st Microsystems and Nanoelectronics Research Conference  
field of logic design and verification.  ...  This paper outlines the MBAC tool for the generation of assertion checkers in hardware.  ...  When simulation times become excessive, designs are often emulated in custom hardware in order to run orders of magnitude faster than in simulators.  ... 
doi:10.1109/mnrc.2008.4683387 fatcat:ir6crrkn4bfu3fjagngsruwhiu
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