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Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
[chapter]
1999
Lecture Notes in Computer Science
Preserved Fulltext
In combination with abstractions, we show that our method can be used to rectify large circuits. ...
In this paper, we present a method for localizing and correcting errors in combinatorial circuits for which equivalence checking has failed. ...
In this paper, we present a method for localizing and correcting errors in combinatorial circuits based on Boolean decomposition and abstraction. ...
doi:10.1007/3-540-48153-2_13
fatcat:6syr6t5abnbyxbtcgxym4yqpva
Abstracts of Current Computer Literature
1969
IEEE transactions on computers
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Compilers and Executive
Systems Using Boolean Program Mod-
els 6929
-see also Monitor Systems, Supervisory
Systems
F
Failures
Correction of Errors Due to Component
Failure in Logic Circuits ...
Diagnosis, Tests
Circuits
Residue Arithmetic Unit Using Digital
Balanced Magnetic Circuits 6917
Correction of Errors Due to Component
Failure in Logic Circuits Using Trip-
lication or Codes 6918 ...
doi:10.1109/t-c.1969.222770
fatcat:3u7q7ac3b5hx5fdffcemcrpsay
Abstracts of Current Computer Literature
1970
IEEE transactions on computers
Preserved Fulltext
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7940
Correction
Essential Hazard Correction in Asynchron-
ous Switching Circuits Without Using De-
lay Elements 7921
-see also Error
D
Data
Exercises for Sampling Distribution and
Data Analysis ...
Operations In-
volved in Division 7925
Use of Boolean Transition Matrices in Com-
piling with High Speed Error Diagnostics
7944
Error Estimates for Real Eigenvalues and
Eigenvectors of Matrices Using ...
doi:10.1109/t-c.1970.223067
fatcat:fmxgtckr5vcivhopuosht7gszu
Verification of electronic systems
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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In fact, formal verification is unthinkable without complete formalization and the use of abstraction to make it feasible on large designs. ...
errors. ...
doi:10.1145/240518.240539
dblp:conf/dac/Sangiovanni-VincentelliMS96
fatcat:52fgmr2625ebvfemmbmaizxzbu
Validating PowerPC microprocessor custom memories
2000
IEEE Design & Test of Computers
Preserved Fulltext
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Acknowledgments We thank the entire project and tools teams at Somerset, Motorola, for their cooperation and commitment to the successful conclusion of this project. ...
Boolean equivalence checking tools are used routinely to verify equivalence between RTL, gate-, and switch-level models of standard library cells and custom-designed circuits. ...
These tools operate by extracting a Boolean function, representing cones of logic from these descriptions (which are at different levels of abstraction) and then comparing their stable outputs. ...
doi:10.1109/54.895007
fatcat:t3w2vughyzem5ot2okcxnb43hm
Logic Synthesis for Established and Emerging Computing
2019
Proceedings of the IEEE
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of limited size todayas well as creating new and more powerful heuristics based on problem decomposition. ...
A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly-which is computationally possible for instances ...
We consider these circuits as atomic primitives, because we want to use an abstraction of the underlying computation valid in a large class of technologies. ...
doi:10.1109/jproc.2018.2869760
fatcat:e2fqalmxlfg65lsewf5c26qwry
Page 1281 of Mathematical Reviews Vol. 50, Issue 4
[page]
1975
Mathematical Reviews
Preserved Fulltext
The Internet Archive has digitized a microfilm copy of this work. It may be possible to borrow a copy for reading.
Applications are discussed in Chapter 6 by showing how LSCs can be used in the multiplication and division of polynomials, in computation, over Galois fields, in counting, in error detection and correction ...
decomposition of Ashenhurst, Curtis and Povarov. ...
A Methodology for Large-Scale Hardware Verification
[chapter]
2000
Lecture Notes in Computer Science
Preserved Fulltext
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This provides a systematic but flexible framework within which to organize the activities undertaken in large-scale verification efforts and to structure the associated code and proof-script artifacts. ...
We illustrate the methodology-which has has proved highly effective in large-scale industrial trials-with the verification of an IEEEcompliant, extended precision floating-point adder. ...
Acknowledgments Ching-Tsun Chou, Limor Fix, Brian Moore, and Eli Singerman made helpful comments on a draft of this paper. Thanks are also due to the anonymous referees for their comments. ...
doi:10.1007/3-540-40922-x_17
fatcat:rogl6mf6mfelvp3d3n3qlmihvm
An industrially effective environment for formal hardware verification
2005
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described. ...
Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight ...
The authors are particularly grateful to the users of Forte at Intel and to the Intel design teams who supplied case studies for their own example verifications. ...
doi:10.1109/tcad.2005.850814
fatcat:rxashd5osrhcjky5mgq2jsodk4
Relational STE and theorem proving for formal verification of industrial circuit designs
2013
2013 Formal Methods in Computer-Aided Design
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We illustrate the effectiveness of this combination of technologies by describing a general framework, accessible to non-experts, that is widely used for verification and regression validation of integer ...
Model checking by symbolic trajectory evaluation, orchestrated in a flexible functional-programming framework, is a well-established technology for correctness verification of industrial-scale circuit ...
For example, the computation may require use of a parametric representation of boolean functions [26] , a specific circuit abstraction method, or certain simulation or constraint satisfaction engines: ...
doi:10.1109/fmcad.2013.6679397
fatcat:76aebjztijc5tmbhzzixkjtuwu
Programming quantum computers using design automation
2018
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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We present and use two tool flows which invoke RevKit. ...
With the rapid growth of qubit numbers and coherence times comes the increasingly difficult challenge of quantum program compilation. ...
ACKNOWLEDGMENTS We thank the QuArC team for useful discussions. Circuits were typeset using q|pic by Tom Draper and Sandy Kutin. ...
doi:10.23919/date.2018.8341993
dblp:conf/date/SoekenHR18
fatcat:usexjb63ejhcljjevwn35b3xk4
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
[chapter]
1998
Lecture Notes in Computer Science
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Our abstraction and encoding techniques result in an automatic symmetry reduction and allow the control and forwarding logic of the actual circuit to be used unmodified. ...
We present a way to abstract functional units in symbolic simulation of actual circuits, thus achieving the effect of uninterpreted functions at the bit-level. ...
However, their tool requires an abstract model of the circuit, leaving room for errors in its description and raising concerns about the correctness of the actual processor, given the correctness of its ...
doi:10.1007/3-540-49519-3_3
fatcat:3yyh2pdvo5hjvbp77hucnwu33y
Abstracts of Current Computer Literature
1969
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
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the Union of a Large
Number of Events 6338
Synthesis of Logical Nets Consisting of
NOR Units 6341
Analysis of Errors in Logic Circuits Using
the Boolean Difference 6342
Use of Miniature Fluidic ...
Resolvents
6410
-see also Algebralc Equations, Boolean,
Integral Equations
Error
Analysis of Errors in Logic Circuits
Using the Boolean Difference 6342
Analysis of Implementation Errors in
Digital ...
doi:10.1109/t-c.1969.222537
fatcat:yogv2lr73be65iqipqwh3bmem4
Abstracts of Current Computer Literature
1970
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Through a number theoretic investigation, a large class of arithmetic codes for single iterative error correction are developed. ...
Automation 7805
Correction
Simple Decoding Method for a General Mul-
tiple Error Correction 7743
Error Correction in High Speed Arithmetic
7744
Spelling Error Correction in Compilers and
Operating ...
doi:10.1109/t-c.1970.223012
fatcat:r5fw2k62rfhphcyztzcnhldnry
Meta-functional Languages for Hardware Design and Verification
2010
2010 Third International Conference on Advances in Circuits, Electronics and Micro-electronics
Preserved Fulltext
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We illustrate the use of these techniques in supporting circuit placement techniques and automatic model checking of hardware compiler invariants. ...
We show how this approach aids the development, analysis and manipulation of embedded objects, whilst at the same time we keep meta-programming features largely invisible to the hardware designer. ...
In the case of regular circuits, concise descriptions in the host language can be used to describe large, complex circuits, using modularity and abstraction techniques from the host language. ...
doi:10.1109/cenics.2010.15
fatcat:g6tavhdw4nacffxdmdmdkxtdpu
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