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Multilevel symmetry-constraint generation for retargeting large analog layouts
2006
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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required for retargeting an analog-to-digital converter layout. ...
Index Terms-Analog integrated circuit (IC), device matching, IC layout, layout automation. ...
Law for valuable discussions on the design and layout of the analog portion of the ADC. ...
doi:10.1109/tcad.2005.855982
fatcat:tctvgcplzzej3n4x7ocgobuwdq
Correct-by-construction layout-centric retargeting of large analog designs
2004
Proceedings of the 41st annual conference on Design automation - DAC '04
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From an existing layout representation, an analog circuit is retargeted to different processes and performances; the corresponding correct-byconstruction layouts are generated automatically and have performances ...
Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. ...
Arsyn automatically synthesizes the analog circuit meeting the required design specifications. The device sizes generated by Arsyn are fed to the layout generator. ...
doi:10.1145/996566.996609
dblp:conf/dac/BhattacharyaJHS04
fatcat:pjqtd334y5f2jh7z3j6tws7rha
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements ...
ANALOG/RF LAYOUT RETARGETING An automatic analog/RF layout retargeting algorithm has been proposed in [6, 7] . ...
doi:10.1145/1233501.1233570
dblp:conf/iccad/JangkrajarngZBKS06
fatcat:xf5dahmkordxvnhe6rle3twp2i
Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements ...
ANALOG/RF LAYOUT RETARGETING An automatic analog/RF layout retargeting algorithm has been proposed in [6, 7] . ...
doi:10.1109/iccad.2006.320056
fatcat:zdazrlmjtrgs7e665sqwan2vfy
IPRAIL—intellectual property reuse-based analog IC layout automation
2003
Integration
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This paper presents a computer-aided design tool, IPRAIL, which automatically retargets existing analog layouts for technology migration and new specifications. ...
IPRAIL automatically extracts analog circuit and layout intellectual properties as templates, incorporates new technology design rules and device sizes, and generates fully functional layouts. ...
ACKNOWLEDGEMENTS The authors would like to thank Youcef Bourai and Bo Wan for their participation in the early phase of the IPRAIL project, and also Kiyong Choi and Jinho Park for valuable discussions ...
doi:10.1016/j.vlsi.2003.08.004
fatcat:rmbn44j7sjb7bokxw2mtg4p7cu
State-of-the-Art on Analog Layout Automation
[chapter]
2016
Analog Integrated Circuit Design Automation
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layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
Finally, the available commercial solutions for analog layout automation are outlined. ...
A template-based generation is used by Intellectual Property Reuse-based Analog IC Layout (IPRAIL) [21] to automatically extract the knowledge embedded in an already made layout, and use it for retargeting ...
doi:10.1007/978-3-319-34060-9_2
fatcat:7flyp6nwd5aprexg2ccab4abau
State of the Art on Analog Layout Automation
[chapter]
2012
SpringerBriefs in Applied Sciences and Technology
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layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
Finally, the available commercial solutions for analog layout automation are outlined. ...
A template-based generation is used by Intellectual Property Reuse-based Analog IC Layout (IPRAIL) [21] to automatically extract the knowledge embedded in an already made layout, and use it for retargeting ...
doi:10.1007/978-3-642-33146-6_2
fatcat:miizfmqdqbd67azo7hb3j72xna
LAYGEN II
2012
Proceedings of the fourteenth international conference on Genetic and evolutionary computation conference - GECCO '12
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The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre® design rule check tool. ...
This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. ...
A template-based generation is used by IPRAIL (Intellectual Property Reuse-based Analog IC Layout) [15] to automatically extract the knowledge embedded in an already made layout, and use it for retargeting ...
doi:10.1145/2330163.2330319
dblp:conf/gecco/MartinsLH12
fatcat:h7spco4qzje7pk2ptw36oiirki
A tool for the automatic generation and analysis of regular analog layout modules
2019
Integration
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This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of seriesconnected or stacked devices, for the ...
Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database. ...
Each layout version is included in a database and used for the generation of an analog layout library. ...
doi:10.1016/j.vlsi.2018.11.005
fatcat:xdznzlrjkbb6lap46wtokeipoa
Automatic generation of hierarchical placement rules for analog integrated circuits
2010
Proceedings of the 19th international symposium on Physical design - ISPD '10
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TCAD'08] Enumeration of placements of fundamental module sets Enhanced Shape Functions Good for semi-automatic layout generation • High flexibility • Enhanced shape function for each node of hierarchy ...
"symmetrical" routing requires
"symmetrical" placement
I n
I p
O p
O n
[Cohn et al.: Analog Device-Level Layout Automation'94]
State of the Art
• Sensitivity analysis
-Parasitic devices ...
doi:10.1145/1735023.1735039
dblp:conf/ispd/EickSGS10
fatcat:zukcrge7mjcmxbsekfzsojcvnq
Generator based approach for analog circuit and layout design and optimization
2011
2011 Design, Automation & Test in Europe
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Layout generation remains a critical bottleneck in analog circuit design. ...
This paper presents a new methodology for layout generation of analog circuits that is based on a modular circuit design and a so-called "executable design flow description". ...
The authors would like to thank their colleagues at Fraunhofer IIS for providing the example circuit as well as Karl-Heinz Rooch (Fraunhofer IIS/EAS), Harald Bothe (IP GEN), and Stefan Jäkel (ZMDI) for ...
doi:10.1109/date.2011.5763267
dblp:conf/date/GraupnerJW11
fatcat:4uaz7rvccnhqbpyaknojyttz4i
Constrained sampling for image retargeting
2008
2008 IEEE International Conference on Multimedia and Expo
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In this paper, we present a new approach for retargeting large images to mobile devices with small screens. ...
As the core of image retargeting, information fidelity is adequately considered in terms of reservations of salient regions, edge integrity, and image layout. ...
Image layout In general, image layout mainly comprises image composition and relative positions of objects. ...
doi:10.1109/icme.2008.4607705
dblp:conf/icmcs/RenGWZ08
fatcat:eqmn5ocyqvdtznhgqxhzjdq3m4
Introduction to the special issue on SMACD 2015
2016
Integration
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A novel identification technique for the extraction of lumped circuit models of general distributed or stray devices is presented in the ninth paper, written by Antonio Luchetta et al. ...
Ahmet Unutulmaz et al. present, in the seventh paper, a declarative language (LDS) intended to code analog layout templates that can be used for layout-aware circuit synthesis. ...
doi:10.1016/j.vlsi.2016.09.001
fatcat:g7yrdepkfbd4pkb7sobjmwavve
KOAN/ANAGRAM II: new tools for device-level analog placement and routing
1991
IEEE Journal of Solid-State Circuits
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A block place-and-route style from macrocell digital IC's has recently emerged as a viable methodology for the automatic layout of custom analog cells. ...
This paper describes KOAN and ANAGRAM 11, new tools for device-level analog placement and routing. ...
The areas of the automatically generated cell and the manually generated cell were 25872 and 32430 p m 2 respectively. An automatic layout for a much more complex op amp appears in Fig. 10 . ...
doi:10.1109/4.75012
fatcat:l5chscqhpfeivfig7yehaoy2e4
Introduction to the special issue on SMACD 2012
2013
Analog Integrated Circuits and Signal Processing
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A novel identification technique for the extraction of lumped circuit models of general distributed or stray devices is presented in the ninth paper, written by Antonio Luchetta et al. ...
Ahmet Unutulmaz et al. present, in the seventh paper, a declarative language (LDS) intended to code analog layout templates that can be used for layout-aware circuit synthesis. ...
doi:10.1007/s10470-013-0227-3
fatcat:xr4g75jmxnhh7ncchrvrsjrcgy
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