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A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

Sameh Asaad, José Tierno, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin Parker, Thomas Roewer, Proshanta Saha, Todd Takken
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
In this paper, we describe a cycle-accurate and cyclereproducible large-scale FPGA platform that is designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor  ...  This paper discusses the challenges for constructing such largescale FPGA platforms, including design partitioning, clocking & synchronization, and debugging support, as well as our approach for addressing  ...  This approach usually involves designing a custom board that will deploy the minimum number of FPGA devices required to map the design at hand.  ... 
doi:10.1145/2145694.2145720 dblp:conf/fpga/AsaadBBHKPRSTT12 fatcat:dtcqzyjhizg3tejrhxgx7wj3x4

IP delivery for FPGAs using Applets and JHDL

Michael J. Wirthlin, Brian McMurtrey
2002 Proceedings - Design Automation Conference  
The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser.  ...  Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of applicationspecific circuits.  ...  These designs range in complexity from small, single-chip controllers to large, multi-FPGA designs for automatic target recognition and sonar beamforming.  ... 
doi:10.1145/513921.513922 fatcat:t2orqecx5jcalonftp2nykyrbi

IP delivery for FPGAs using applets and JHDL

M.J. Wirthlin, B. McMurtrey
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser.  ...  Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of applicationspecific circuits.  ...  These designs range in complexity from small, single-chip controllers to large, multi-FPGA designs for automatic target recognition and sonar beamforming.  ... 
doi:10.1109/dac.2002.1012584 fatcat:x7c65t5jnnaltluoasl5divega

IP delivery for FPGAs using Applets and JHDL

Michael J. Wirthlin, Brian McMurtrey
2002 Proceedings - Design Automation Conference  
The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser.  ...  Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of applicationspecific circuits.  ...  These designs range in complexity from small, single-chip controllers to large, multi-FPGA designs for automatic target recognition and sonar beamforming.  ... 
doi:10.1145/513918.513922 dblp:conf/dac/WirthlinM02 fatcat:rbhrwxhj5zgvlinspjuon5zcla

A Novel Fingerprint SoC with Bit Serial FPGA Engine

Yiwen Wang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda
2005 IPSJ Digital Courier  
Example application is to realize fingerprint authentication system in a chip. The paper presents secondly design flow for SoC, including a full-custom block.  ...  The paper presents firstly a novel system-on-chip (SoC) architecure consisting of a 32-bit RISC processor, on-chip memory, state-of-the art IPs and embedded full-custom bit serial FPGA (BSFPGA) I/O interface  ...  At the start phase, in order to run the whole system synthesis and static timing analysis (STA) before BSFPGA full-custom design is finished, A quick timing model (QTM) of BSF-PGA is created.  ... 
doi:10.2197/ipsjdc.1.226 fatcat:orfssl3bevapzjcilrzv7fndvm

Go Ahead: A Partial Reconfiguration Framework

Christian Beckhoff, Dirk Koch, Jim Torresen
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
GOAHEAD enables the building of flexible systems for integrating many reconfigurable modules very efficiently into a system.  ...  In this paper, we introduce the tool GOAHEAD that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs.  ...  When following a reconfigurable design flow, this results in a fully routed netlist. This netlist could even be simulated (post place & route simulation).  ... 
doi:10.1109/fccm.2012.17 dblp:conf/fccm/BeckhoffKT12 fatcat:zgry7hjcm5dj7mt3oob2eqdbmy

Generation and Validation of Custom Multiplication IP Blocks from the Web [article]

Minas Dasygenis
2015 arXiv   pre-print
Automatic generation of custom VHDL models for performing this operation, allows the designer to achieve a time efficient design space exploration.  ...  Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 589 Mhz.  ...  Pihl et al [16] , Wen-Jong [8] and Abke et al [1] created tools to optimize arithmetic circuits either for FPGA or for VLSI ASIC design flows.  ... 
arXiv:1502.07454v1 fatcat:ur4ikvb3vndkvft5me5femqbqy

Intel nehalem processor core made FPGA synthesizable

Graham Schelle, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang, Jamison Collins, Ethan Schuchman, Perrry Wang, Xiang Zou, Gautham Chinya, Ralf Plate (+2 others)
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs.  ...  Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch  ...  to thank Joe Schutz, Steve Pawlowski, Justin Rattner, Glenn Hinton, Rani Borkar, Shekhar Borkar, Jim Held, Jag Keshava, Belliappa Kuttanna, Chris Weaver, Elinora Yoeli, Pat Stolt and Ketan Paranjape for  ... 
doi:10.1145/1723112.1723116 dblp:conf/fpga/SchelleCSWZCPMOHSBSW10 fatcat:rim6adpnardmdptcchem5y3d2q

Hierarchical reconfiguration of FPGAs

Dirk Koch, Christian Beckhoff
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to  ...  For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and  ...  MULTICORE CASE STUDY We created a reconfigurable multicore case study for demonstrating the design flow for implementing hierarchical partial reconfiguration (see Section II).  ... 
doi:10.1109/fpl.2014.6927491 dblp:conf/fpl/KochB14 fatcat:t2q2jjhlgna5zbo7nqgn3vkipq

FPGA-based rapid prototyping of digital signal processing systems

K. Banovic, M.A.S. Khalid, E. Abdel-Raheem
2005 48th Midwest Symposium on Circuits and Systems, 2005.  
A survey of DSP design methodologies and computeraided design (CAD) tools for FPGAs is presented, which includes methodologies for standard register-transfer-level (RTL) design, system-level design, and  ...  The application of FPGA emulation systems as a platform for rapid prototyping is addressed and future trends of FPGA-based DSP systems are suggested. 0-7803-9197-7/05/$20.00  ...  This creates a gap between algorithmic design and hardware specification within the design flow, which prevents it from being a true top-down design flow.  ... 
doi:10.1109/mwscas.2005.1594184 fatcat:fdheh3b6djegtkeo3prgjejqfa

Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs

Jose Luis Nunez-Yanez
2015 IEEE transactions on computers  
We present a novel design flow that creates the adaptive power architecture starting from an user design in RTL format. 3.  ...  The pulse mode architecture is evaluated in a custom design FPGA device fabricated using 90nm CMOS process.  ... 
doi:10.1109/tc.2014.2365963 fatcat:fpbjprqw3rgb3nkcj53zs37cy4

Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors

Jose Nunez-Yanez
2017 Microprocessors and microsystems  
This paper presents an enhanced tool flow and hardware to allow a host CPU to exploit the timing margins available on a FPGA fabric to improve its performance or reduce its energy and power requirements  ...  The hardware netlist is processed and in-situ detectors are automatically added to monitor and pre-detect timing failures occurring in the critical path flip-flops.  ...  Acknowledgements: We would like to thank the support received from EPSRC for this work which is part of the ENPOWER (EP/L00321X/1) and the ENEAC (EP/N002539/1) projects.  ... 
doi:10.1016/j.micpro.2017.04.021 fatcat:elvgoy5je5gurkb3eaova37lzm

Implementation of BEE

Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications.  ...  In addition, a parallel path to the prototyping flow leads automatically from the top-level description to an ASIC implementation.  ...  The main goal of the BEE design flow is to enable communication algorithm designers to use system-level design tools to create hardware designs that can be both implemented rapidly on a BEE system and  ... 
doi:10.1145/611817.611832 dblp:conf/fpga/ChangKRB03 fatcat:jiyy4c3uefh7xjwsmi3iw2hzvq

Implementation of BEE

Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications.  ...  In addition, a parallel path to the prototyping flow leads automatically from the top-level description to an ASIC implementation.  ...  The main goal of the BEE design flow is to enable communication algorithm designers to use system-level design tools to create hardware designs that can be both implemented rapidly on a BEE system and  ... 
doi:10.1145/611831.611832 fatcat:blksbyxv2bh3dpmp5q5l65aqra

Logic emulation with virtual wires

J. Babb, R. Tessier, M. Dahl, S.Z. Hanono, D.M. Hoki, A. Agarwal
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45%.  ...  20K-gate boards.  ...  The input, a netlist of the logic design to be emulated, is transformed into a multi-FPGA configuration bit stream to be downloaded onto the emulator.  ... 
doi:10.1109/43.640619 fatcat:xslresgiivbi7pjbujhtecivii
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