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Automated microprocessor stressmark generation

Ajay M. Joshi, Lieven Eeckhout, Lizy K. John, Ciji Isen
2008 High-Performance Computer Architecture  
Leveraging this abstract workload modeling approach, we propose StressMaker, a framework that uses machine learning for the automated generation of stressmarks.  ...  A comparison with an exhaustive exploration of a large power design space demonstrates that StressMaker is very effective in automatically generating stressmarks in a limited amount of time.  ...  In this paper we propose StressMaker, a framework for the automated generation of stressmarks.  ... 
doi:10.1109/hpca.2008.4658642 dblp:conf/hpca/JoshiEJI08 fatcat:nkjhslscozcs5fpvc3te2kxebu

Automated di/dt stressmark generation for microprocessor power delivery networks

Youngtaek Kim, Lizy Kurian John
2011 IEEE/ACM International Symposium on Low Power Electronics and Design  
In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power delivery network.  ...  In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies.  ...  a Genetic Algorithm to generate a benchmark that creates a maximum voltage droop in a given microprocessor and PDN.  Our automated framework reduces designers' time to generate a hand-coded di/dt stressmark  ... 
doi:10.1109/islped.2011.5993645 fatcat:nr7s2judcfbhbla26tvnogzixe

AUDIT: Stress Testing the Automatic Way

Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael Schulte, W. Lloyd Bircher, Madhu S. Sibi Govindan
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
is an automation framework for stressmark generation • Target: Multi-core processor • Finding Max.  ...  Voltage Droop: Genetic Algorithm with hardware measurement generates effective di/dt stressmarks in a short time • Larger voltage droop than other benchmarks/stressmarks • Higher voltage failure points  ...  benchmarks: ineffective to test voltage margin -Generating and running di/dt stressmarks AUDIT: AUtomated DI/dT Stressmark Generation AUDIT -Genetic Algorithm: Operational Concept AUDIT: AUtomated DI/dT  ... 
doi:10.1109/micro.2012.28 dblp:conf/micro/KimJPMSBG12 fatcat:nprlpjid7ff53dvjsaqdicz3au

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Arun Arvind Nair, Lizy Kurian John, Lieven Eeckhout
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
generating a stressmark that approaches the maximum SER of an out-of-order processor.  ...  Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages  ...  The significant contributions of this work are as follows: 1) We develop a flexible and automated methodology to generate an AVF stressmark.  ... 
doi:10.1109/micro.2010.34 dblp:conf/micro/NairJE10 fatcat:ewityvqpdnayjipwaizpr7iksa

Finding Stress Patterns in Microprocessor Workloads [chapter]

Frederik Vandeputte, Lieven Eeckhout
2009 Lecture Notes in Computer Science  
These workloads range from benchmarks that represent typical behavior up to hand-tuned stress benchmarks (so called stressmarks) that stress the microprocessor to its extreme power consumption.  ...  This paper closes the gap between these two extremes by studying techniques for the automated identification of stress patterns (worst-case application behaviors) in typical workloads.  ...  These stressmarks are typically hand-tuned, and push the microprocessor to its extremes in order to understand the microprocessor's worst-case behavior.  ... 
doi:10.1007/978-3-540-92990-1_13 fatcat:zcs3yxbxyjdsvjg7cuaeo6va5q

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose, Timothy J. Slegel, Gerard Salem, Sean Carey, Richard F. Rizzolo, Thomas Strach
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
We develop a systematic methodology to generate noise stressmarks.  ...  We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree  ...  Section III presents the stressmark generation methodology. Section IV details the experimental set up.  ... 
doi:10.1109/micro.2014.12 dblp:conf/micro/BertranBBSSCRS14 fatcat:6rgemig45rfp7gpu3smzxs6a4y

Robust power management in the IBM z13

T. Webel, P. M. Lobo, R. Bertran, G. M. Salem, M. Allen-Ware, R. Rizzolo, S. M. Carey, T. Strach, A. Buyuktosunoglu, C. Lefurgy, P. Bose, R. Nigaglioni (+3 others)
2015 IBM Journal of Research and Development  
It also enables rapid bring-up through automated generation of microbenchmarks in contrast with manual generation.  ...  Automation in stressmark generation has been attempted by other research groups, but as discussed in [12] , MicroProbe has significant new features, tested in real machine contexts, that have not been  ... 
doi:10.1147/jrd.2015.2446872 fatcat:xgg5ohzx5vgmhhm6hcbhbabv34

System-level max power (SYMPO)

Karthik Ganesan, Jungho Jo, W. Lloyd Bircher, Dimitris Kaseridis, Zhibin Yu, Lizy K. John
2010 Proceedings of the 19th international conference on Parallel architectures and compilation techniques - PACT '10  
We also show that the power viruses generated in the Alpha ISA consume 9-24% more power compared to the previous approach of stressmark generation.  ...  These stressmarks, also called power viruses, are very tedious to generate and require significant domain knowledge.  ...  [15] introduced the idea of automatic stressmark generation using an abstract workload generator.  ... 
doi:10.1145/1854273.1854282 dblp:conf/IEEEpact/GanesanJBKYJ10 fatcat:kw5ovydmfrb6vkxcru5hbcsnxy

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017 ACM SIGOPS Operating Systems Review  
Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average.  ...  In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak  ...  Kim et al. used a genetic algorithm to automatically generate stressmarks that target maximum di/dt-induced voltage droop for a microprocessor [26] .  ... 
doi:10.1145/3093315.3037711 fatcat:jcqmt4nj5nhyhg2mqhq6txbhrq

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017 Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '17  
Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average.  ...  In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak  ...  Kim et al. used a genetic algorithm to automatically generate stressmarks that target maximum di/dt-induced voltage droop for a microprocessor [26] .  ... 
doi:10.1145/3037697.3037711 dblp:conf/asplos/CherupalliDY0S17 fatcat:765liw2yubedpeh5n42y322hni

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017 SIGPLAN notices  
Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average.  ...  In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak  ...  Kim et al. used a genetic algorithm to automatically generate stressmarks that target maximum di/dt-induced voltage droop for a microprocessor [26] .  ... 
doi:10.1145/3093336.3037711 fatcat:e6cw3uwjaja3re7rwqyinazl2q

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017 SIGARCH Computer Architecture News  
Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average.  ...  In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak  ...  Kim et al. used a genetic algorithm to automatically generate stressmarks that target maximum di/dt-induced voltage droop for a microprocessor [26] .  ... 
doi:10.1145/3093337.3037711 fatcat:i46wzvf37rg6neihh77vjhyhby

Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017 ACM Transactions on Computer Systems  
Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average.  ...  In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak  ...  Kim et al. used a genetic algorithm to automatically generate stressmarks that target maximum di/dt-induced voltage droop for a microprocessor [26] .  ... 
doi:10.1145/3148052 fatcat:uliax4vsyzayldkvszj5f6lvxq

Recent thermal management techniques for microprocessors

Joonho Kong, Sung Woo Chung, Kevin Skadron
2012 ACM Computing Surveys  
The overall objective of this survey is to give microprocessor designers a broad perspective on various aspects of designing thermal-aware microprocessors and to guide future thermal management studies  ...  Floorplanning covers a range of thermal-aware floorplanning techniques for 2D and 3D microprocessors.  ...  Joshi et al. [2008] proposed an automated stressmark generation technique.  ... 
doi:10.1145/2187671.2187675 fatcat:bsvvqax2rbftxivi555mzzc7uy

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems

R. Bertran, Y. Sugawara, H. M. Jacobson, A. Buyuktosunoglu, P. Bose
2013 IBM Journal of Research and Development  
Automated max-power stressmark generation methodologies are therefore crucial in this regard.  ...  of energy-related stressmarks. • Systematic Maximum power stressmark generation method.  ...  POTRA: A Framework for Building Power Models for Next Generation Multicore Architectures [ Nacho Navarro is Associate Professor at the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain, since  ... 
doi:10.1147/jrd.2012.2227580 fatcat:e2yb6krghzdvfkaavxy7ha3li4
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