Filters








30 Hits in 8.8 sec

Computer-aided design of analog and mixed-signal integrated circuits

G.G.E. Gielen, R.A. Rutenbar
2000 Proceedings of the IEEE  
Keywords-Analog and mixed-signal computer-aided design (CAD), analog and mixed-signal integrated circuits, analog circuit and layout synthesis, analog design automation, circuit simulation and modeling  ...  This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout  ...  There are not yet any robust commercial CAD tools to support or automate analog circuit design apart from circuit simulators (in most cases, some flavor of the ubiquitous SPICE simulator [6] ) and layout  ... 
doi:10.1109/5.899053 fatcat:2kjzezalevhuzayfrkykyvm5py

ComputerAided Design of Analog and MixedSignal Integrated Circuits [chapter]

2009 Computer-Aided Design of Analog Integrated Circuits and Systems  
Keywords-Analog and mixed-signal computer-aided design (CAD), analog and mixed-signal integrated circuits, analog circuit and layout synthesis, analog design automation, circuit simulation and modeling  ...  This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout  ...  There are not yet any robust commercial CAD tools to support or automate analog circuit design apart from circuit simulators (in most cases, some flavor of the ubiquitous SPICE simulator [6] ) and layout  ... 
doi:10.1109/9780470544310.ch1 fatcat:nz4on5owvvdxbneeuh3aqrkkfe

Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming

T. McConaghy, G.G.E. Gielen
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents CAFFEINE, a method to automatically generate compact, interpretable symbolic performance models of analog circuits with no prior specification of an equation template.  ...  CAFFEINE uses SPICE simulation data, to model arbitrary nonlinear circuits and circuit characteristics.  ...  Symbolic analysis extracts the expressions via topological analysis of the circuit, whereas symbolic modeling extracts the expressions by using SPICE simulation data.  ... 
doi:10.1109/tcad.2009.2021034 fatcat:xdktqiomdnf5lncq7tt2lo25ti

Behavioral Modeling of Mixed-Mode Integrated Circuits [chapter]

Esteban Tlelo-Cuautle, Elyoenai Martnez-Romero, Carlos Snchez-Lpez, Francisco V., Sheldon X.-D., Peng Li, Mourad Fakhfakh
2011 Advances in Analog Circuits  
In fact, the circuit design cycle covers different stages which can be performed in a hierarchical way, from the specifications down to the layout, and from the extraction of layout-parasitics up to the  ...  Extraction of poles and zeros from symbolic transfer functions is subject to strong limitations for two reasons: 1.  ... 
doi:10.5772/15864 fatcat:vu2m7tgsm5dg5objbjotyfy24y

Synthesis of high-performance analog circuits in ASTRX/OBLX

E.S. Ochotta, R.A. Rutenbar, L.R. Carley
1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic.  ...  This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem.  ...  Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. Mukherjee.  ... 
doi:10.1109/43.489099 fatcat:awvixpettzc5rpw6gssllbktn4

Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX [chapter]

2009 Computer-Aided Design of Analog Integrated Circuits and Systems  
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic.  ...  This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem.  ...  Kirkpatrick of IBM, and their coresearchers at Camegie Mellon: R. Rohrer and his AWE group, R. Harjani, P. C. Maulik, B. Stanisic, and particularly, T. Mukherjee.  ... 
doi:10.1109/9780470544310.ch14 fatcat:uchovdny5bgbfcmtbnmglshqia

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet Roychowdhury
2007 Proceedings of the IEEE  
We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit.  ...  successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems.  ...  McConaghy, who have contributed largely to the work on hierarchical synthesis and performance modeling.  ... 
doi:10.1109/jproc.2006.889371 fatcat:nsxteyaqpzfl5no5v5iboedrgy

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We develop an efficient yet accurate heuristic pruning rule to approximate the computationally expensive statistical problem.  ...  We also show that our approaches have polynomial time complexity with respect to the net-size.  ...  with SPICE.  ... 
doi:10.1109/tcad.2006.884869 fatcat:yknw47ynyvhvhhqfzixmkaxj6m

An integrated CAD system for algorithm-specific IC design

C.B. Shung, R. Jain, K. Rimey, E. Wang, M.B. Srivastava, B.C. Richards, E. Lettang, S. Khalid Azim, L. Thon, P.N. Hilfinger, J.M. Rabaey, R.W. Brodersen
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The silicon assembler then translates the filled-out structural description into a physical layout and with the aid of simulation tools, the user can fine tune the data path by iterating this process.  ...  A number of algorithm-specific IC's designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip will be described.  ...  ACKNOWLEDGMENT The authors are grateful to the following students of the University of California at Berkeley and Los Angeles who have contributed to the development of LAGER and provided valuable feedback  ... 
doi:10.1109/43.75628 fatcat:t6tomh5imrhcbamc4uubb3hxku

Freeze

Yuantao Peng, Xun Liu
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
In comparison with the state-of-the-art low-power repeater insertion schemes, FREEZE requires 5.8 times fewer iterations on the average, achieving up to 27 times speedup with even better power savings.  ...  Experimental results demonstrate the high effectiveness of our approach.  ...  The circuit parameters of repeaters and interconnects, e.g., unit-length wire capacitance and unit-width gate capacitance, were extracted from TSMC technology files and calibrated using SPICE simulations  ... 
doi:10.1145/1065579.1065794 dblp:conf/dac/PengL05 fatcat:u6k5ad2onrcotf3b6hc6e3gomy

A tutorial introduction to research on analog and mixed-signal circuit testing

L.S. Milor
1998 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem.  ...  This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.  ...  missing or extra material in a given layer of a layout and extracts the impact on circuit topology [25] , [26] .  ... 
doi:10.1109/82.728852 fatcat:vfon3dk5cvhddpfutzx5dajsau

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Yuantao Peng, Xun Liu
2005 Proceedings. 42nd Design Automation Conference, 2005.  
In comparison with the state-of-the-art low-power repeater insertion schemes, FREEZE requires 5.8 times fewer iterations on the average, achieving up to 27 times speedup with even better power savings.  ...  Experimental results demonstrate the high effectiveness of our approach.  ...  The circuit parameters of repeaters and interconnects, e.g., unit-length wire capacitance and unit-width gate capacitance, were extracted from TSMC technology files and calibrated using SPICE simulations  ... 
doi:10.1109/dac.2005.193927 fatcat:tudkznlbonew7hugqwass4zxxq

Comprehensive frequency-dependent substrate noise analysis using boundary element methods

Hongmei Li, J. Carballido, H.H. Yu, V.I. Okhmatovski, E. Rosenbaum, A.C. Cangellaris
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.  
Examples of model calibration, both directly from layout and as model-order reduction of a given inductance matrix, are presented for simple wiring structures.  ...  Element Equivalent Circuits (PEEC) extracted from the multi-layer interconnects and transistor level transient analysis via SPICE-like tools.  ...  subjecting the resulting RTL circuits to logic synthesis and layout.  ... 
doi:10.1109/iccad.2002.1167506 fatcat:xsqqw7lg2zcbnk5y7uyqfhebnq

Trends on the application of emerging nonvolatile memory to processors and programmable devices

Lionel Torres, Raphael Martins Brum, Luis Vitorio Cargnini, Gilles Sassatelli
2013 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)  
., "Trends on the application of emerging nonvolatile memory to processors and programmable devices," Circuits and Sys-Torres, L.; Brum, R.M.; Guillemenet, Y.; Sassatelli, G.; Cargnini, L.V., "Evaluation  ...  of hybrid MRAM/CMOS cells for reconfigurable computing," New Circuits and Systems Zhao, W.S.; Zhang, Y.; Lakys, Y.; Klein, J-O; Etiemble, D.; Revelosona, D.; Chappert, C.; Torres, L.; Cargnini, L.V.;  ...  characterize (with real spice) write _ library -overwrite $model sram.  ... 
doi:10.1109/iscas.2013.6571792 dblp:conf/iscas/TorresBCS13 fatcat:aommoaizybhufp76nxuappbxby

Message from the general chair

Benjamin C. Lee
2015 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
Compared with the best system from CoNLL-2011, which employs a rule-based method, our system shows competitive performance.  ...  We propose a joint learning model which combines pairwise classification and mention clustering with Markov logic.  ...  street to the front gate of a house.  ... 
doi:10.1109/ispass.2015.7095776 dblp:conf/ispass/Lee15 fatcat:ehbed6nl6barfgs6pzwcvwxria
« Previous Showing results 1 — 15 out of 30 results