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Automated RTL Generator for Optimized Flop Repeater Network

Rahul Bhatt, Shweta Sharma, Shyam A
2018 EAI Endorsed Transactions on Cloud Systems  
This paper will show how we are creating optimized tree structure based on mathematical techniques and generating automated RTL for such repeater flop module.  ...  The flop repeater structure for each signal should be optimized so that it has minimum number of flops and timing is also met, to achieve desired targets for timing, area and power.  ...  We would like to acknowledge the effort of Aman Aggarwal, who had helped us to develop few VBA macros for tool.  ... 
doi:10.4108/eai.13-7-2018.162634 fatcat:s5m75fc66jcnrn6js7lvzwlimq

Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors

V. Viswanath, J.A. Abraham, W.A. Hunt
2006 Proceedings of the Design Automation & Test in Europe Conference  
Our technique automatically annotates existing RTL code to optimize the circuit for lowering power dissipated by switching activity.  ...  We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation.  ...  Figure 1 . 1 Overview of the Instruction-driven Slicing Algorithm for RTL. flops, then the algorithm adds to the existing logic in an optimized fashion.  ... 
doi:10.1109/date.2006.243858 dblp:conf/date/ViswanathAJ06 fatcat:ls5edfnbfbeuniowtdviq4xn3y

A physical design study of fabscalar-generated superscalar cores

Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes.  ...  The output of FabScalar is a synthesizable register-transfer-level (RTL) description of the desired core.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their valuable feedback. This research was supported by NSF grant CCF-0811707 and gifts from Intel and IBM.  ... 
doi:10.1109/vlsi-soc.2012.6379024 dblp:conf/vlsi/ChoudharyDR12 fatcat:bivkardchrbshm65jjtx3gv6yy

A physical design study of fabscalar-generated superscalar cores

Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes.  ...  The output of FabScalar is a synthesizable register-transfer-level (RTL) description of the desired core.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their valuable feedback. This research was supported by NSF grant CCF-0811707 and gifts from Intel and IBM.  ... 
doi:10.1109/vlsi-soc.2012.7332095 fatcat:okptkwlzkrblbgjh475sowengm

ORION 2.0: A Power-Area Simulator for Interconnection Networks

Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We expect that this analysis can be provided for better 3-D designs.  ...  In order to mitigate the impact two techniques may be used: 1) design optimization such as insert buffers to reduce the increased delay due to intertier connections and 2) insert registers in the path  ...  Using automation scripts, we vary the above parameters and generate corresponding RTL for each combination of parameters. We then synthesize the RTL codes using TSMC 65 nm general-purpose library.  ... 
doi:10.1109/tvlsi.2010.2091686 fatcat:r765hgkhunafjele7v25gmtklu

Automatic RTL Generation Tool of FPGAs for DNNs

Seojin Jang, Wei Liu, Sangun Park, Yongbeom Cho
2022 Electronics  
With the increasing use of multi-purpose artificial intelligence of things (AIOT) devices, embedded field-programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration  ...  We also introduce a long short-term memory (LSTM)-based model to predict performance and generate a DNN model that suits the developer requirements automatically.  ...  of FPGA design. (3) Highly optimized RTL network components can be automatically generated for building DNN layers.  ... 
doi:10.3390/electronics11030402 fatcat:mex52yf5brho3pwi4xubdauqte

Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers

G. Subash Chandar, S. Vaideeswaran
2001 Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01  
The verification cycle time reduction and the salient features of an automated methodology that was developed specifically for our DSP core are described.  ...  Also, a set of RTL coding guidelines to make the design equivalence checker friendly is detailed.  ...  Though coming up with generic automated efficient flow is difficult, it is possible to optimize different phases with the pre-knowledge of the abstracts on which EC is performed. E.g.  ... 
doi:10.1145/370155.370316 dblp:conf/aspdac/ChandarV01 fatcat:dbx3mvifrnfyddcnzpnxa6qp64

Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip [chapter]

Arya Wicaksana, Dareen Kusuma Halim, Dicky Hartono, Felix Lokananta, Sze-Wei Lee, Mow-Song Ng, Chong-Ming Tang
2018 Application Specific Integrated Circuits - Technologies, Digital Systems and Design Methodologies [Working Title]  
The use of electronic design automation (EDA) software during each step of the design methodology is also presented.  ...  This system specification is the entry point in the proposed ASIC design methodology and the final design step of the methodology is tape-out for fabrication.  ...  The automated routing process is done in three incremental steps. Leakage-power is the optimization target for the initial routing step.  ... 
doi:10.5772/intechopen.79855 fatcat:vff3ewqmmzfnrpxgr2eyo2g5ye

Is overlay error more important than interconnect variations in double patterning?

Kwangok Jeong, Andrew B. Kahng, Rasit O. Topaloglu
2009 Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09  
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores.  ...  To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.  ...  Hangsheng Wang of Freescale for his technical support of the original ORION code, and Tushar Krishna of Princeton University for assisting with validation.  ... 
doi:10.1145/1572471.1572474 dblp:conf/slip/JeongKT09 fatcat:s4wnrttfdffjlmwbqrptbb7xke

Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy
2000 Proceedings of the 2000 international symposium on Physical design - ISPD '00  
In this paper, we describe a methodology for inserting repeaters into the RTL, Layout, Floorplan and Fullchip timing databases of the Itanium™ processor.  ...  It is a distributed network of resistances and capacitance. Typically once these netcells are generated they are fed back into the timing model.  ...  Repeaters and RTL There are two types of repeaters, those that change the functionality of the signal, such as latches or flops, and those that don't, such as buffers.  ... 
doi:10.1145/332357.332383 dblp:conf/ispd/McInerneyLHCBM00 fatcat:kyrowv2ygvh67acgjto7jfkf4a

An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2)

Tim Johnson, Umesh Nawathe
2007 Proceedings of the 2007 international symposium on Physical design - ISPD '07  
CMT (Chip Multi-Threading) processor optimized for Space, Power, and Performance (SWaP)  ...  better route optimization. • Datapaths: > Pseudo-verilog inferred datapath rows (macros). > Embedded flop headers and mux-selects. > Rows relatively placed within the DP regions. > Minimum sized cells  ...  dft/reset timing verification. • Automated substitution flow to swap in Low-Vt cells for critical path optimization. > What-if analysis enables quick min/max convergence. • Automatic slack-based 'fix'  ... 
doi:10.1145/1231996.1232000 dblp:conf/ispd/JohnsonN07 fatcat:7bz26tk7pbbq7gu6tmxadt2toe

Design methodology for semi custom processor cores

Victor Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
optimizations spanning multiple levels of the design hierarchy.  ...  We describe a semi-custom design methodology for embedded processor cores that was prototyped through the development of a low power high performance DSP core.  ...  Grouping of latches for clock splitters To allow the opportunity of licensing RTL as a soft-core, and to simplify code maintenance, edge-triggered behavioral flip flops are used in the VHDL.  ... 
doi:10.1145/988952.989060 dblp:conf/glvlsi/ZyubanAFHLM04 fatcat:x36zxgn4ibc5lis5gigdrr2fwq

RHNAS: Realizable Hardware and Neural Architecture Search [article]

Yash Akhauri, Adithya Niranjan, J. Pablo Muñoz, Suvadeep Banerjee, Abhijit Davare, Pasquale Cocchini, Anton A. Sorokin, Ravi Iyer, Nilesh Jain
2021 arXiv   pre-print
Fully differentiable co-design has reduced the resource requirements for discovering optimized NN-HW configurations, but fail to adapt to general hardware accelerator search spaces.  ...  RHNAS is a method that combines reinforcement learning for hardware optimization with differentiable neural architecture search.  ...  Since our RL HW optimizer agent is disentangled from the NN architecture search, we can take the resultant network from the NAS algorithm with no simulation/FLOPs loss and generate HW optimized for that  ... 
arXiv:2106.09180v1 fatcat:j7zj3qvzjrgbvp3dh2tyg5snai

System Design Methodologies [chapter]

Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, Gunar Schirner
2009 Embedded System Design  
In this chapter we will look at different design methodologies, or design flows, for multi-processor systems.  ...  Design methodologies have evolved together with manufacturing technology, design complexity, and design automation.  ...  The design decomposition or synthesis has to be repeated over and over again without designers really knowing whether optimization is going in the right direction.  ... 
doi:10.1007/978-1-4419-0504-8_2 fatcat:2dxlvw5rgzfgppudvy5p5oo5zq

Design of Higher Order Matched FIR Filter Using Odd and Even Phase Process

V. Magesh, N. Duraipandian
2022 Intelligent Automation and Soft Computing  
The current research paper discusses the implementation of higher order-matched filter design using odd and even phase processes for efficient area and time delay reduction.  ...  This process gets repeated until all the coefficients are computed in the optimized path that require minimum number of shifters and adders.  ...  Fig. 12 shows the Register Transfer Logic (RTL) view for the proposed system whereas Fig. 13 shows a detailed view of RTL for the proposed system.  ... 
doi:10.32604/iasc.2022.020552 fatcat:sdjrcubzmjgn5avelp6kqydrhq
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