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Accounting for various register allocation schemes during post-synthesis verification of RTL designs

Nazanin Mansouri, Ranga Vemuri
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization schemes commonly found  ...  We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs.  ...  Formal verification systems in general, can usually verify only a small subset of synthesized designs.  ... 
doi:10.1145/307418.307493 fatcat:lfxzf277ivhj3b7lt5mi7oglbu

High-level Synthesis Integrated Verification

M. Dossis
2015 Engineering, Technology & Applied Science Research  
Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution.  ...  It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification.  ...  Simulating the RTL for reassurance In order to reassure in practice the formal nature of the synthesis process the generated RTL for the line draw app. is simulated as shown in Figure 6 and Figure 7  ... 
doi:10.48084/etasr.596 fatcat:ocbsn6gyyvb4fewihqp2qwus2i

High-Level Synthesis: A Practical Perspective

Michael Dossis
2013 Advances in Robotics & Automation  
Adv Robot Autom 3: 123. Abstract The current complexity of custom and embedded core or IP integrated electronics demand for a new generation of automated system design and development methods.  ...  An alternative HLS toolset is presented that the author has developed and which is based on formal methods, thus it guarandees the correctness of the synthesized hardware and system.  ...  After the tests were coded and verified in ADA they were synthesized into VHDL/Verilog RTL. Since the C-cubed tools are based on formal techniques there is no need to simulate the generated RTL.  ... 
doi:10.4172/2168-9695.1000123 fatcat:vcjlem6nqvgtbkykoi7iurf5xe

Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers

G. Subash Chandar, S. Vaideeswaran
2001 Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01  
Formal verification plays an important role in the verification of complex processors.  ...  The verification cycle time reduction and the salient features of an automated methodology that was developed specifically for our DSP core are described.  ...  Formal Verification has the potential to reduce the verification time. Formal Verification (FV) is a mathematical way of proving the functional correctness of a design.  ... 
doi:10.1145/370155.370316 dblp:conf/aspdac/ChandarV01 fatcat:dbx3mvifrnfyddcnzpnxa6qp64

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Michael Dossis
2017 International Robotics & Automation Journal  
One serious problem of automated high-level synthesis tools is their inability of at least difficulty to use for low, bit level functions such as signal processing blocks.  ...  Design environments and automated CAD systems are proliferated nowadays with various preferences and restrictions in their work environments.  ...  Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment 5/5 Copyright: ©2017 Dossis Conclusion and Future Work Formal and rapid automated synthesis and automated formal verification  ... 
doi:10.15406/iratj.2017.02.00029 fatcat:7zpbc5ibfrgelgfiqfed33a3me

Are Hls Tools Healthy? The C-Cubed Project

M. Dossis, G. Dimitriou
2015 Zenodo  
thus they guarantee the correctness of the synthesized hardware implementations.  ...  The present article is a practical perspective of the required fully automated and formal tools, which are needed to constitute integral parts in Electronic Design Automation (EDA) flows.  ...  Since the C-Cubed transformations utilize formal techniques there is no need to simulate the generated RTL.  ... 
doi:10.5281/zenodo.16989 fatcat:fcirdvxuwvgjhd73eqcqr554f4

Functional Equivalence Verification Tools in High-Level Synthesis Flows

A. Mathur, M. Fujita, E. Clarke, P. Urard
2009 IEEE Design & Test of Computers  
High-Level Synthesis Editor's note: High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification  ...  SEC in HLS flows Deployment of SEC in HLS flows can be automated because the HLS tools can automatically generate the wrappers and interface mapping needed for SEC.  ...  He has received several awards from major Japanese scientific societies for his work in formal verification and logic synthesis. He has a PhD in information engineering from the University of Tokyo.  ... 
doi:10.1109/mdt.2009.79 fatcat:jmkzzjmujndl5iexr2u4zeupyu

RTL C-based methodology for designing and verifying a multi-threaded processor

L. Semeria, A. Seawright, R. Mehra, D. Ng, A. Ekanayake, B. Pangrle
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1109/dac.2002.1012606 fatcat:2otw277idfbg7lcekm6vlecmhm

RTL c-based methodology for designing and verifying a multi-threaded processor

Luc Sèmèria, Renu Mehra, Barry Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
2002 Proceedings - Design Automation Conference  
A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1145/513918.513951 dblp:conf/dac/SemeriaMPESN02 fatcat:3w7rm3b2yrg7ljvc2uc5rkyeha

RTL c-based methodology for designing and verifying a multi-threaded processor

Luc Sèmèria, Renu Mehra, Barry Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
2002 Proceedings - Design Automation Conference  
A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1145/513950.513951 fatcat:s3h3m2nudjfitphlzfkubh4mvq

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

Michael F. Dossis
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
Using compiler-generators and logic programming techniques, provably-correct hardware compilation flow is achieved.  ...  The hardware compilation runs are completed in orders-of-magnitude less time than that which would be needed by even very experienced HDL designers to implement the same applications in RTL code.  ...  It is argued here, that the presented methodology reduces the specification, design, verification and implementation cycles of computing products by orders of magnitude, due to the formal and automated  ... 
doi:10.1109/isvlsi.2010.40 dblp:conf/isvlsi/Dossis10 fatcat:iyr7ugsao5axnccjthhf54phta

Integrating formal verification and high-level processor pipeline synthesis

Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien L. Lu
2011 2011 IEEE 9th Symposium on Application Specific Processors (SASP)  
This paper presents our effort in integrating fully automated formal verification with a high-level processor pipeline synthesis framework.  ...  The paper reports case studies of applying this integrated framework to synthesize and formally verify pipelined RISC and CISC processors.  ...  Clarke from School of Computer Science at Carnegie Mellon, Scott Robinson from Intel, and our colleagues in the Computer Architecture Lab at Carnegie Mellon for their interaction and feedback.  ... 
doi:10.1109/sasp.2011.5941073 dblp:conf/sasp/NurvitadhiHKL11 fatcat:xrnee2lta5eexexddvf5ndr2di

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Michael Dossis
2013 Advances in Robotics & Automation  
Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction.  ...  Citation: Dossis M (2014) Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques. Adv Robot Autom 3: 121.  ...  Arbitrary and general input ADA code is synthesized into functionally-equivalent RTL VHDL/Verilog hardware implementation.  ... 
doi:10.4172/2168-9695.1000121 fatcat:6vwlruh4yfg2bi6dhyhmz2uoy4

Challenges in processor modeling and validation [Guest Editors' introduction]

P. Bose, T.M. Conte, T.M. Austin
1999 IEEE Micro  
Acknowledgments We thank all the anonymous referees for their help in reviewing the articles submitted for this special issue and Ken Sakamura, IEEE Micro Editor-in-Chief, for his help and support.  ...  This formalism is shown to point the way toward the automated synthesis and verification of complex microarchitectures.  ...  Validation issues Current microprocessor design teams use a combination of simulation-based and formal verification techniques to validate (functionally) the RTL and pre-RTL models.  ... 
doi:10.1109/mm.1999.768495 fatcat:jfxhc7zbsrhcrfdzr575xsnp2a

Optimizing blocks in an SoC using symbolic code-statement reachability analysis

Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Our symbolic codestatement reachability analysis can extract don't-care conditions from constrained-random testbenches or other design blocks to identify unreachable conditional blocks in the design code  ...  Our results show that we can optimize designs under different constraints and provide additional flexibility for SoC design flows.  ...  The advantage of utilizing reachability analysis at the RTL for design optimization is twofold. (1) A few lines of RTL code can be synthesized into numerous gates.  ... 
doi:10.1109/aspdac.2010.5419784 dblp:conf/aspdac/ChouCK10 fatcat:b5a4zueojzgexacy3p3hachh3a
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