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Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin
2020 The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays  
To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically generate both FPGA- and ASIC-based DNN chip implementation given DNNs from machine learning  ...  Experimental results show that our Chip Predictor's predicted performance differs from real-measured ones by < 10% when validated using 15 DNN models and 4 platforms (edge-FPGA/TPU/GPU and ASIC).  ...  ACKNOWLEDGMENTS This work is supported in part by the NSF RTML grant (1937592), the IBM-Illinois Center for Cognitive Computing System Research (C3SR), and  ... 
doi:10.1145/3373087.3375306 dblp:conf/fpga/0011ZHZZWLGCL20 fatcat:wuhsatu7sjhmpbamwfkml4t6ma

EH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture Search [article]

Qian Jiang, Xiaofan Zhang, Deming Chen, Minh N. Do, Raymond A. Yeh
2021 arXiv   pre-print
We also introduce E2E-Perf, an end-to-end hardware benchmarking tool for customized accelerators.  ...  Experiments on CIFAR10 and ImageNet show that EH-DNAS improves the hardware performance by an average of 1.4× on customized accelerators and 1.6× on existing hardware processors while maintaining the classification  ...  AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. In Proc. FPGA, 2020. [37] Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, and Deming Chen.  ... 
arXiv:2111.12299v1 fatcat:hrtt7wr6ifep5nrhlruyeqajre