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Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols

Dana Vantrease, Mikko H. Lipasti, Nathan Binkert
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
This paper advocates Atomic Coherence, a framework that simplifies cache coherence protocol specification, design, and verification by decoupling races from the protocol's operation.  ...  Atomic Coherence requires conflicting coherence requests to the same addresses be serialized with a mutex before they are issued. Once issued, requests follow a predictable race-free path.  ...  CONCLUSION In this paper, we advocate nanophotonic support for building high-performance simple atomic protocols.  ... 
doi:10.1109/hpca.2011.5749723 dblp:conf/hpca/VantreaseLB11 fatcat:qjeosry5gnf2jog7gu7mmske6e

A composite and scalable cache coherence protocol for large scale CMPs

Yi Xu, Yu Du, Youtao Zhang, Jun Yang
2011 Proceedings of the international conference on Supercomputing - ICS '11  
, we propose a composite cache coherence (C 3 ) protocol that benefits from direct cache-to-cache accesses as in snoopy protocol and small amount of cache probing as in directory protocol.  ...  However, it remains a big challenge to efficiently support cache coherence for large scale CMPs.  ...  Atomic coherence [50] serializes the transactions with mutexes to reduce additional racing transitions in directory protocol but brings performance penalty due to atomic coherence and large number of  ... 
doi:10.1145/1995896.1995941 dblp:conf/ics/XuDZY11 fatcat:opqhm3oagjgjnl6gptirr4zsii

Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges

Yi Xu, Sudeep Pasricha
2014 IEEE design & test  
Nanophotonic network protocols Designing hardware cache coherence protocols for future multicore computing is challenging.  ...  To maintain the ordering in unordered network, atomic coherence [6] serializes the transactions with mutexes (optical tokens) to reduce additional racing transitions and ensure correctness in a directory  ... 
doi:10.1109/mdat.2014.2332153 fatcat:dzgwiooy3zbyhkf2rgvegfeium

Exploiting New Interconnect Technologies in On-Chip Communication

John Kim, Kiyoung Choi, Gabriel Loh
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
The continuing scaling of transistors has increased the number of cores available in current processors, and the number of cores is expected to continue to increase.  ...  In this paper, we investigate alternative interconnect technologies that can be exploited to address the communication challenges in future manycore processor.  ...  For example, in addition to using the nanophotonic for global data communication or arbitration as discussed earlier, the nanophotonic can be leveraged to build a race-free cache coherence protocol [92  ... 
doi:10.1109/jetcas.2012.2201031 fatcat:3arzyh25zrcybaqc3sqlocus2q

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Sergi Abadal, Josep Torrellas, Eduard Alarcon, Albert Cabellos-Aparicio
2018 IEEE Transactions on Parallel and Distributed Systems  
In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility.  ...  With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology.  ...  For instance, cache coherence is currently implemented via directory-based schemes that limit the use of multicast to the invalidation of cache blocks on a shared write.  ... 
doi:10.1109/tpds.2017.2764901 fatcat:ddncdg63cjdmteew434colaiwu