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Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of highperformance testers and  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/513918.514010 dblp:conf/dac/KrsticLCCD02 fatcat:wanljgmetzfb7pncwaxcsm3x5e

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of highperformance testers and  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/514009.514010 fatcat:2nluc3xsorg2zegsuuliffxv7i

AMBA: enabling reusable on-chip designs

D. Flynn
1997 IEEE Micro  
The harness supports the testing of an on-chip module using canned vectors.  ...  Cached processor cores may then run at a higher multiple of the bus clock. • Wide on-chip DRAM. Several ARM semiconductor licensees use embedded DRAM technology.  ... 
doi:10.1109/40.612211 fatcat:4ieg4x6t4nbwvlek74mgkzjsd4

Software-based self-testing methodology for processor cores

Li Chen, S. Dey
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
At-speed testing of gigahertz processors using external testers may not be technically and economically feasible.  ...  Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed.  ...  Sekar for their help with the picoJava processor core.  ... 
doi:10.1109/43.913755 fatcat:ors6roeymfgq5mmozi2mgg52te

Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

Anuja Sehgal, Krishnendu Chakrabarty
2007 IEEE transactions on computers  
Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture and the Tiger system from Teradyne.  ...  The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different  ...  A preliminary version of this paper appeared in the Proceedings of the IEEE Design, Automation and Test in Europe (DATE) Conference, pp. 422-427, 2004.  ... 
doi:10.1109/tc.2007.250628 fatcat:5aplodnpzneufb5zpbthrmvhgy

Instruction-level DFT for testing processor and IP cores in system-on-a-chip

Wei-Cheng Lai, Kwang-Ting Cheng
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination  ...  We propose a DfT methodology to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core.  ...  To self-test the DLX core, we can first load the test program from an external tester into the on-chip memory. Then, the DLX core executes the test program at-speed.  ... 
doi:10.1145/378239.378282 dblp:conf/dac/LaiC01 fatcat:jcqs5a6xp5gqnia7x54ooddz2m

Low-Cost Test of Embedded RF/Analog/Mixed-Signal Circuits inSOPs

S.S. Akbay, A. Halder, A. Chatterjee, D. Keezer
2004 IEEE Transactions on Advanced Packaging  
Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages very difficult.  ...  To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed.  ...  and micro-electro-mechanical-systems (MEMS) as an interface with the outer world.  ... 
doi:10.1109/tadvp.2004.828819 fatcat:xhuzcymqijb7ro7h3ygsp5ruym

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability

H. Kikukawa, S. Tomishima, T. Tsuji, T. Kawasaki, S. Sakamoto, M. Ishikawa, W. Abe, H. Tanizaki, H. Kato, T. Uchikoba, T. Inokuchi, M. Senoh (+7 others)
2002 IEEE Journal of Solid-State Circuits  
We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment.  ...  This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-m triple-well 4-level Cu embedded DRAM technology.  ...  The DRAM core in the system LSI chip wasted time during the burn-in test of the system LSI chip.  ... 
doi:10.1109/jssc.2002.1015693 fatcat:mnguu22ptzhzxomgqpzbqzjg3a

Testing embedded-core-based system chips

Y. Zorian, E.J. Marinissen, S. Dey
1999 Computer  
This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug.  ...  Advances in semiconductor process and design technology enable the design of complex system chips.  ...  We thank Robert Arendsen and Maurice Lousberg of Philips for providing us with useful feedback on draft versions of this paper.  ... 
doi:10.1109/2.769444 fatcat:vd7nx4xhwvglnfiqnu7fpiczku

An novel methodology for reducing SoC test data volume on FPGA-based testers

P. Bernardi, M. Sonza Reorda
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Low-Cost test methodologies for Systems-on-Chip are increasingly popular.  ...  The proposed method relies on test pattern compression at system level and it does not address core level pattern manipulation, as several other previously published works do.  ...  With the advent of Systems-on-Chip (SoCs), the term Low-Cost is commonly used to classify a set of strategies and equipments that exploit Design-for-Testability (DfT) features included on-chip for reducing  ... 
doi:10.1145/1403375.1403423 fatcat:62cw22krsrf4nirzbbb7lfqqqe

2001 technology roadmap for semiconductors

A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian
2002 Computer  
Acknowledgments We acknowledge the efforts of the many individuals who contributed to making the 2001 edition of The International Technology Roadmap for Semiconductors a successful endeavor.  ...  While semiconductor off-chip speeds have improved at 30 percent per year, tester accuracy has improved at a rate of only 12 percent per year.  ...  Larger portions of test will require expanded DFT techniques and protocols-for example, IEEE P1500-as well as significant use of BIST or embedded software-based self-testing to counteract the growth in  ... 
doi:10.1109/2.976918 fatcat:mv3q7f3l2zfjng2i5rvipkdhsi

Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor

P. Yeung, A. Torres, P. Batra
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In this paper, we shall discuss the test infrastructure and methodologies used to accelerate bring-up and in-system silicon characterization for high-speed mixed-signal I/O.  ...  As a case study, we shall illustrate these techniques used in the development of the Rambus FlexIO™ processor bus and XIO™ memory interface used on the first generation Cell processor (aka Cell Broadband  ...  Acknowledgements We extend our thanks and gratitude to Wai-Yeung Yip, David Nguyen, Kenyon Han, Melissa Frank, Paula Tostado and Keisuke Saito of Rambus Inc. for reviewing the paper. References  ... 
doi:10.1109/date.2007.364681 dblp:conf/date/YeungTB07 fatcat:oe3qm36zxjf5vmnv5y3az25rfu

FPGA Implementation of Memory Bists using Single Interface

2020 International journal of recent technology and engineering  
The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications.  ...  To overcome those drawbacks, pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm.  ...  In this paper MBIST developed based on proposed Pipelined March-c approach which provides a suitable framework for testing of memories, which is embedded in System on Chip (SOCs) and Memory cores.  ... 
doi:10.35940/ijrte.b3975.099320 fatcat:eu54wgk325dh7juuhwubo3hiii

Using a soft core in a SoC design: experiences with picoJava

S. Dey, D. Panigrahi, Li Chen, C.N. Taylor, K. Sekar, P. Sanchez
2000 IEEE Design & Test of Computers  
Acknowledgments We would like to thank Sun Microsystems for open licensing of the picoJava core, and the sponsors of the SRC Cu-Design Contest for access to the 0.18um Cu technology.  ...  This work is funded by Marco/Darpa Gigascale Silicon Research Center (GSRC), UC Micro, NEC USA and SRC.  ...  Instead of relying on an external tester for applying tests to the scan chains, LBIST generates test vectors on-chip using a linear feedback shift register (LFSR).  ... 
doi:10.1109/54.867896 fatcat:x52yvcjg4jbwvc3szbbrouowcm

Software-Based Self-Testing of Embedded Processors [chapter]

Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, George Xenoulis
2007 Processor Design  
Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in  ...  Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or performance overheads.  ...  System development based on the use of a core-based architecture, where cores are interconnected by an industry standard on-chip bus, is very common.  ... 
doi:10.1007/978-1-4020-5530-0_20 fatcat:fe55ksgbxfh3jhjw2rf7e4dpxa
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