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Modeling Algorithm Performance on Highly-threaded Many-core Architectures

Lin Ma
We do not try to model the Intel Xeon Phi, due to its limited use of threading for latency hiding.  ...  Stranneheim et al. observed a 21-fold speedup when FACS was executed on a 2.8 GHz Intel Xeon processor.  ... 
doi:10.7936/k73x84sg fatcat:qm7rhseiibew3ldj6mdnlwr7vi

Dagstuhl Reports, Volume 3, Issue 09, September 2013, Complete Issue [article]

We developed a template library that provides TBB-like parallel patterns that are executed in a hybrid fashion on the host and one or more Xeon Phi coprocessors simultaneously.  ...  Our initial suggests how we might use these to explore the landscape of systems and algorithms that might be possible in the future.  ...  We also present preliminary results for the Fujitsu FX10, the Sandy Bridge, and the Xeon Phi.  ... 
doi:10.4230/dagrep.3.9 fatcat:oilweqoffjbx7bjnxvg6vorrzu