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Asymmetry-Aware Work-Stealing Runtimes

Christopher Torng, Moyang Wang, Christopher Batten
2016 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)  
In this paper, we propose asymmetry-aware work-stealing (AAWS) runtimes, which are carefully designed to exploit both the static and dynamic asymmetry in modern systems.  ...  We use a vertically integrated research methodology spanning software, architecture, and VLSI to make the case that holistically combining static asymmetry, dynamic asymmetry, and work-stealing runtimes  ...  ACKNOWLEDGMENTS This work was supported in part by NSF CAREER Award #1149464, AFOSR YIP Award #FA9550-15-1-0194, and donations from Intel and Synopsys.  ... 
doi:10.1109/isca.2016.14 dblp:conf/isca/TorngWB16 fatcat:x6ekct3uwzg5vpig33njscm2n4

Asymmetry-aware work-stealing runtimes

Christopher Torng, Moyang Wang, Christopher Batten
2016 SIGARCH Computer Architecture News  
In this paper, we propose asymmetry-aware work-stealing (AAWS) runtimes, which are carefully designed to exploit both the static and dynamic asymmetry in modern systems.  ...  We use a vertically integrated research methodology spanning software, architecture, and VLSI to make the case that holistically combining static asymmetry, dynamic asymmetry, and work-stealing runtimes  ...  ACKNOWLEDGMENTS This work was supported in part by NSF CAREER Award #1149464, AFOSR YIP Award #FA9550-15-1-0194, and donations from Intel and Synopsys.  ... 
doi:10.1145/3007787.3001142 fatcat:roxlav6fera3baw37un4d7ih5a

Scheduling Task-parallel Applications in Dynamically Asymmetric Environments [article]

Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericas
2020 arXiv   pre-print
Our proposed task scheduler dynamically learns the performance characteristics of the underlying platform and uses this knowledge to devise better schedules aware of dynamic performance asymmetry, hence  ...  In this work, we study how application-level scheduling techniques can leverage moldability (i.e. flexibility to work as either single-threaded or multithreaded task) and explicit knowledge on task criticality  ...  The random work-stealing scheduler (RWS), behaves as a decentralized greedy scheduler where each thread owns a work-stealing queue.  ... 
arXiv:2009.00915v2 fatcat:xspjxhx6hrhajkzxpvypa6kmyu

Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations

Luis Costero, Francisco D. Igual, Katzalin Olcoz, Sandra Catalán, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí
2017 Parallel Computing  
strategies embedded into a runtime framework.  ...  Furthermore, this solution also outperforms an ad-hoc asymmetry-aware scheduler furnished with sophisticated scheduling techniques.  ...  with no special modifications. • Any existing scheduling policy (e.g. cache-aware mapping or work stealing) in an asymmetry-agnostic runtime, or any enhancement technique, will directly impact the performance  ... 
doi:10.1016/j.parco.2017.06.002 fatcat:ncuqf3ts45a7nbpheisiie2yzy

Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors [article]

Jyothi Krishna V S, Shankar Balachandran
2018 arXiv   pre-print
asymmetry and improve the runtime efficiency.  ...  In this paper, we propose a hardware-aware Compiler Enhanced Scheduling (CES) where the common compiler transformations are coupled with compiler added scheduling commands to take advantage of the hardware  ...  The hardware-asymmetry aware CES compiler is aimed at reducing this gap. CES optimizes the parallel execution time by reducing the disparity in individual thread running time.  ... 
arXiv:1808.06074v1 fatcat:u3saoouzjveynmvrwn2ora7r64

Bandwidth and Locality Aware Task-stealing for Manycore Architectures with Bandwidth-Asymmetric Memory

Han Zhao, Quan Chen, Yuxian Qiu, Ming Wu, Yao Shen, Jingwen Leng, Chao Li, Minyi Guo
2018 ACM Transactions on Architecture and Code Optimization (TACO)  
To solve the two problems, we propose a Bandwidth and Locality Aware Task-stealing (BATS) system, which consists of an HBM-aware data allocator, a bandwidth-aware traffic balancer, and a hierarchical task-stealing  ...  The hierarchical scheduler improves data locality at runtime without a priori program knowledge.  ...  The runtime system has three components: an HBMaware data allocator, a bandwidth-aware traffic balancer, and a hierarchical task-stealing scheduler.  ... 
doi:10.1145/3291058 fatcat:tp6lvtiwhrehhpjdh4m3hb4bja

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moreto, Marc Casas
2018 IEEE Transactions on Parallel and Distributed Systems  
For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data  ...  ACKNOWLEDGMENTS This work has been supported by the Spanish Government (Severo Ochoa grants SEV2015-0493), by the Spanish Ministry of Science and Innovation (contracts TIN2015-  ...  If an execution suffers from load imbalance the Nanos++ runtime system overcomes this via NUMA aware work stealing [1] .  ... 
doi:10.1109/tpds.2017.2787123 fatcat:kz7gsqv5zvawvh7uulewkoiawe

Mitigating inefficient task mappings with an Adaptive Resource-Moldable Scheduler (ARMS) [article]

Mustafa Abduljabbar, Mahmoud Eljammaly, Miquel Pericas
2021 arXiv   pre-print
Compared to previous approaches, ARMS achieves up to 3.5x performance gain over state-of-the-art locality-aware scheduling schemes.  ...  Efficient runtime task scheduling on complex memory hierarchy becomes increasingly important as modern and future High-Performance Computing (HPC) systems are progressively composed of multisocket and  ...  Finally, Section 5 evaluates the scheduler with respect to locality-aware and traditional techniques. Section 6 highlights the related work in the field of locality-aware work-stealing runtimes.  ... 
arXiv:2112.09509v1 fatcat:vidlzdanrvfhfp2nbqmj5kzjdy

Multi-Threaded Dense Linear Algebra Libraries for Low-Power Asymmetric Multicore Processors [article]

Sandra Catalán, José R. Herrero, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí
2015 arXiv   pre-print
In this paper we address this challenge by developing an asymmetry-aware implementation of the BLAS, based on the BLIS framework, and tailored for AMPs equipped with two types of cores: fast/power hungry  ...  Our results on an ARM big.LITTLE processor embedded in the Exynos 5422 SoC, using the asymmetry-aware version of the BLAS and a plain migration of the legacy version of LAPACK, experimentally assess the  ...  However, the application of a runtime to a legacy code is not as simple as it may sound and, as argued in the discussion of related work, the development of asymmetry-aware runtimes is still immature.  ... 
arXiv:1511.02171v1 fatcat:kcuvaisbrrek5iar7l66mmxspe

Application of secretary algorithm to dynamic load balancing in user-space on multicore systems

Teng-Sheng Moh, Kyoung-Hwan Yun
2014 2014 International Conference on High Performance Computing & Simulation (HPCS)  
Both work-sharing and work-stealing require support by compiler and runtime (if not by OS or by application modification).  ...  To address localityobliviousness due to randomized stealing and inflexibility of fixed task scheduling policy (work-first or help-first [10] ), a scalable locality-aware adaptive work-stealing scheduler  ... 
doi:10.1109/hpcsim.2014.6903793 dblp:conf/hpcs/MohY14 fatcat:cghto5lhxjbx5pypzqudnbfgwy

Smartlocks

Jonathan Eastep, David Wingate, Marco D. Santambrogio, Anant Agarwal
2010 Proceeding of the 7th international conference on Autonomic computing - ICAC '10  
This work demonstrates that lock scheduling is important for addressing asymmetries in multicores.  ...  asymmetries in multicores.  ...  Its parallelism employs distributed work queues with work stealing.  ... 
doi:10.1145/1809049.1809079 dblp:conf/icac/EastepWSA10 fatcat:pe4llyq6irehzisczu6wznb7ja

Embracing heterogeneity with dynamic core boosting

Hyoun Kyu Cho, Scott Mahlke
2014 Proceedings of the 11th ACM Conference on Computing Frontiers - CF '14  
DCB coordinates its compiler and runtime to enable asymmetric CMPs to achieve near-optimal utilization of core boosting.  ...  Such an imbalance can be significantly exacerbated by performance asymmetry among cores, which is likely to exist in future generations of chip multiprocessors (CMPs) either for energy efficiency or due  ...  RELATED WORK In this section, we first survey previous work that suggests performance asymmetry in CMPs.  ... 
doi:10.1145/2597917.2597932 dblp:conf/cf/ChoM14 fatcat:tx22yxw3mnbu7dpe5ccwealwua

Rinnegan

Sankaralingam Panneerselvam, Michael Swift
2016 Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16  
The Rinnegan runtime provides a performance model to predict the speedup and overhead of offloading a task.  ...  We built Rinnegan, a Linux kernel extension and runtime library, to perform scheduling and handle task placement in heterogeneous systems.  ...  Acknowledgements This work is supported in part by National Science Foundation (NSF) grants CNS-1302260, CNS-1117280 and CCF-1533885.  ... 
doi:10.1145/2967938.2967964 dblp:conf/IEEEpact/PanneerselvamS16 fatcat:jdb54w3c5nhijlymy6mukdnxly

AASH

Vahid Kazempour, Ali Kamali, Alexandra Fedorova
2010 Proceedings of the 6th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments - VEE '10  
This work for the first time implements simple changes to the hypervisor scheduler, required to make it asymmetry-aware, and evaluates the benefits and overheads of these asymmetryaware mechanisms.  ...  To perform effective matching of threads to cores, the thread scheduler must be asymmetry-aware; and while asymmetry-aware schedulers for operating systems are a well studied topic, asymmetry-awareness  ...  In that case an asymmetry-aware guest OS that interacts with an application runtime environment is required [16] .  ... 
doi:10.1145/1735997.1736011 dblp:conf/vee/KazempourKF10 fatcat:6tmy6mexubbrxgityqhku6tifa

Enabling technologies for self-aware adaptive systems

M D Santambrogio, H Hoffmann, J Eastep, A Agarwal
2010 2010 NASA/ESA Conference on Adaptive Hardware and Systems  
This work presents our vision for self-aware adaptive systems and proposes enabling technologies to address these three challenges.  ...  meet their goals, and c) developing standard techniques that generalize and can be applied to a broad range of self-aware systems.  ...  ACKNOWLEDGMENT We'd like to thank all the many people we worked with over the last two years for all the useful discussions and for their thoughtful ideas. Special thanks to Jason E.  ... 
doi:10.1109/ahs.2010.5546266 dblp:conf/ahs/SantambrogioHEA10 fatcat:pz5qb6oapfczleyvaqpirwmndu
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