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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration

Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatie, Gilles Sassatelli, David Novo, Lionel Torres, Michel Robert
2016 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)  
Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big.LITTLE.  ...  We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.  ...  features two clusters, "big" and "LITTLE", each of which consists of quad Cortex-A15 and quad Cortex-A7 cores respectively.  ... 
doi:10.1109/mcsoc.2016.20 dblp:conf/mcsoc/ButkoBGSNTR16 fatcat:xjme6ttuujdenjaicjb6hir3g4

Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures [article]

Anastasiia Butko, Florent Bruguier, David Novo, Abdoulaye Gamatié, Gilles Sassatelli
2019 arXiv   pre-print
In particular, single-ISA heterogeneous multicore processors such as ARM big.LITTLE have become very attractive since they offer good opportunities in terms of performance and power consumption trade-off  ...  The present paper aims to explore these gains by considering single-ISA heterogeneous multicore architectures including three different types of cores.  ...  The processor features two heterogeneous clusters, "big" and "LITTLE", each of which consists of four Cortex-A15 and four Cortex-A7 cores respectively.  ... 
arXiv:1902.02343v1 fatcat:a5qfw3mtongqxnk2vnvbtgxpci

WAEAS: An optimization scheme of EAS scheduler for wearable applications

Zhan Zhang, Xiang Cong, Wei Feng, Haipeng Zhang, Guodong Fu, Jianyun Chen
2021 Tsinghua Science and Technology  
Workload balancing and task migration are also the important features of multicore scheduling algorithm.  ...  processor; however, the embedded heterogeneous multicore processor is divided into the cluster of big cores and the cluster of little cores, which computing power is different from the other.  ... 
doi:10.26599/tst.2019.9010040 fatcat:pzbxw3f4pbhkxdm26p2calypw4

An Adaptive and Integrated Low-Power Framework for Multicore Mobile Computing

Jongmoo Choi, Bumjong Jung, Yongjae Choi, Seiil Son
2017 Mobile Information Systems  
The key feature of the proposed framework is adaptability.  ...  Employing multicore in mobile computing such as smartphone and IoT (Internet of Things) device is a double-edged sword.  ...  Conflicts of Interest The authors declare that there are no conflicts of interest regarding the publication of this paper. Acknowledgments The  ... 
doi:10.1155/2017/9642958 fatcat:2fhjult6ovd2fpfscke4phvaxq

PMCTrack: Delivering Performance Monitoring Counter Support to the OS Scheduler

J. C. Saez, A. Pousa, R. Rodriíguez-Rodriíguez, F. Castro, M. Prieto-Matias
2016 Computer journal  
In this paper, we analyze different case studies that demonstrate the flexibility, simplicity and powerful features of PMCTrack.  ...  A large body of work has demonstrated that the OS can perform effective runtime optimizations in multicore systems by leveraging performance-counter data.  ...  It has been also supported by a grant scholarship from the University of Costa Rica and the Costa Rican Ministry of Science and Technology MICIT and CONICIT.  ... 
doi:10.1093/comjnl/bxw065 fatcat:swxqcwtm7bcnzah22dy6aevikq

An Evaluation of Coarse-Grained Locking for Multicore Microkernels [article]

Kevin Elphinstone, Amirreza Zarrabi, Adrian Danis, Yanyan Shen, Gernot Heiser
2016 arXiv   pre-print
Our thesis is that on such hardware, a well-designed microkernel, with short system calls, can take advantage of coarse-grained locking on modern hardware, avoid the run-time and complexity cost of multiple  ...  We evaluate performance on two architectures: x86 and ARM MPCore, in the former case also utilising transactional memory (Intel TSX).  ...  ARM platform Our ARM platform is the Sabre Lite, which is based on a Freescale i.MX 6Q SoC, featuring a quad-core ARM Cortex-A9 MPCore processor [Freescale, 2013] .  ... 
arXiv:1609.08372v2 fatcat:erghtyzjrfgwddddefwz45w7ri

Portable performance on asymmetric multicore processors

Ivan Jibaja, Ting Cao, Stephen M. Blackburn, Kathryn S. McKinley
2016 Proceedings of the 2016 International Symposium on Code Generation and Optimization - CGO 2016  
Static and dynamic power constraints are steering chip manufacturers to build single-ISA Asymmetric Multicore Processors (AMPs) with big and small cores.  ...  WASH effectively identifies and optimizes a wider class of workloads than prior work.  ...  Predicting speedup from little to big when the microarchitectures differ is often not possible.  ... 
doi:10.1145/2854038.2854047 dblp:conf/cgo/JibajaCBM16 fatcat:dgdx7swpu5eafhze3wufc5euwu

Energy Discounted Computing on Multicore Smartphones

Meng Zhu, Kai Shen
2016 USENIX Annual Technical Conference  
We show that, for optimal co-run energy discount, the best-effort processing must not elevate the overall system power state (specifically, no reduction of the multicore CPU idle state, no increase of  ...  In addition, we use available ARM performance counters to identify co-run resource contention on the multicore processor and throttle best-effort task when it interferes with interactivity.  ...  Also, chips equipped with CPUs of different micro-architectures (e.g., ARM big-LITTLE) are used to mitigate the performance vs. power dilemma.  ... 
dblp:conf/usenix/ZhuS16 fatcat:crtgvu6jtvhfhbsh36jsgbxxvy

An Intelligent Task Scheduling Mechanism for Autonomous Vehicles via Deep Learning

Gomatheeshwari Balasekaran, Selvakumar Jayakumar, Rocío Pérez de Prado
2021 Energies  
SLFN-EHF task scheduler achieved better results in an average of 98% accuracy, and in an average of 20–27% reduced in execution time and 32–45% in task miss rate metric than conventional methods.  ...  Safe driving is one of the essential concerns of self-driving cars.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/en14061788 fatcat:q7ksrt7tdbbgfckyklcdrjlq5e

Power neutral performance scaling for energy harvesting MP-SoCs

Benjamin J. Fletcher, Domenico Balsamo, Geoff V. Merrett
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017  
To overcome this, large energy buffers such as supercapacitors or batteries are typically incorporated to achieve energy neutral operation, where the energy consumed over a certain period of time is equal  ...  of 69% more instructions compared to existing static approaches.  ...  The processor features 8 CPU cores (4× 'LITTLE' ARM A7 cores and 4× 'big' ARM A15 cores), and operates between 4.1V and 5.7V.  ... 
doi:10.23919/date.2017.7927231 dblp:conf/date/FletcherBM17 fatcat:gdb3epgdz5h7zmbp4btsi7nrzq

Towards Energy-Efficient Heterogeneous Multicore Architectures for Edge Computing

Abdoulaye Gamatie, Guillaume Devic, Gilles Sassatelli, Stefano Bernabovi, Philippe Naudin, Michael Chapman
2019 IEEE Access  
Various heterogeneous multicore designs are developed and prototyped on FPGA for unbiased evaluation.  ...  INDEX TERMS Edge computing, energy-efficiency, heterogeneous multicore architectures, programming model, embedded systems. 49474 2169-3536  ...  ACKNOWLEDGEMENTS The authors would like to thank the referees of IEEE Access for their insightful comments and suggestions that contributed to improve this work.  ... 
doi:10.1109/access.2019.2910932 fatcat:yhnntycuezeolnaxjy2nodzcoy

Multicore enablement for Cyber Physical Systems

Andreas Herkersdorf
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
All leading processor vendors -ARM, Freescale, IBM, Infineon, Intel, MIPS, Nvidia -follow a strictly multicore-oriented strategy.  ...  The focus of the seminar was on the exchange of experiences and discussion of the challenges of reusable and transferable multicore technologies.  ...  with time-predictable execution.  ... 
doi:10.1109/samos.2012.6404198 dblp:conf/samos/Herkersdorf12 fatcat:73whij7ozbfgpimxz4md3f4jii

Energy Efficient and Fault Tolerant Multicore Wireless Sensor Network: E²MWSN

Hong-Ling Shi, Kun Mean Hou, Hai-Ying Zhou, Xing Liu
2011 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing  
Table 6 - 6 17 Key Features of Different Multicore WSN Nodes Chapter 6.  ...  Though dissymmetrical multicore structure will bring a little bit software design complexity, it can help to improve the multicore architecture in all four of these vectors: robustness, power, cost and  ...  The FSMOS is separated into a number of logical modules each provides a set of APIs accessible for the user.  System services provide common functions for all layers, which are necessary for normal stack  ... 
doi:10.1109/wicom.2011.6040317 fatcat:b6qehpnmxjd35go7ycy5v5ru5y

Performance and energy footprint assessment of FPGAs and GPUs on HPC systems using Astrophysics application [article]

David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, Giuliano Taffoni
2020 arXiv   pre-print
We investigate the behavior of the different devices where the high-end GPUs excel in terms of time-to-solution while MPSoC-FPGA systems outperform GPUs in power consumption.  ...  Two of them represent the current HPC systems (Intel-based and equipped with NVIDIA GPUs), one is a micro-cluster based on ARM-MPSoC, and one is a "prototype towards Exascale" equipped with ARM-MPSoCs  ...  This research has been made use of IPython [38] , Scipy [39] , Numpy [37] and MatPlotLib [40] .  ... 
arXiv:2003.03283v2 fatcat:cgsagyvimbhd3pu3cv37q2hfyu

SLOOP

M. Waqar Azhar, Per Stenström, Vassilis Papaefstathiou
2017 ACM Transactions on Architecture and Code Optimization (TACO)  
Such chips feature different types of computing elements, each with different performance/energy tradeoffs (e.g., ARM's big-LITTLE consists of big out-of-order cores and LITTLE in-order cores, GPUs, and  ...  The prediction of the execution time and the QoS requirements are then used to schedule the application on a heterogeneous architecture with big out-of-order cores and small (LITTLE) in-order cores and  ...  run on a real ARM-based big-LITTLE system to quantify the potential of using QoS to save energy by DVFS and core-type scheduling.  ... 
doi:10.1145/3148053 fatcat:3fck2cua6ncz5gwx25y4pm374u
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