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METE
2011
Performance Evaluation Review
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R 2 = 1 − P (ÎP Ci(k) − IP Ci(k)) 2 P (ÎP Ci(k) − IP Ci(avg)) 2 , (11) M AP E = 1 K K X k=1 |Î P Ci(k) − IP Ci(k) IP Ci(k) | . (12)
Dynamics of METE In this set of experimental results, we first show ...
Resource Broker 1 ref ) ( 1 k u 2 ref ) ( 2 k u ) ( 2 k u ) (k u n n ref ) ( 1 k u C1 C2 Cm L1 L1 L1 shared L2 cache to off chip memory ) ( k u n ) 1 ( − k IPC
System Model As mentioned earlier, a feedback ...
doi:10.1145/2007116.2007119
fatcat:ldbk6t5dmzef7g7ddfttvriueq
PSO-GWO Optimized Fractional Order PID based Hybrid Shunt Active Power Filter for Power Quality Improvements
2020
IEEE Access
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(10) . u (t) = K p e (t) + K i t 0 e (t) + K d de (t) dt (10) The above control parameters (K p , K i , K d ) are optimized using PSO, GWO and hybrid PSO-GWO techniques.
B. ...
ASIT MOHANTY (Member, IEEE) was graduated from NIT Durgapur. He is currently with the Electrical Engineering Department, CET, Bhubaneswar. ...
doi:10.1109/access.2020.2988611
fatcat:n2gfzal3nrgbznjfj3xsdwtali
OWL
2013
SIGPLAN notices
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Assume that the size of each CTA is k warps (which is pre-determined for an application kernel). This corresponds to each group having n × k warps. ...
It means that, the minimum value of n × k should be 5. Since k depends on the GPGPU application kernel, the group size can vary for different application kernels. ...
doi:10.1145/2499368.2451158
fatcat:shmoske2xrejpgycwdmrvl3n3u
MIRA
2008
SIGARCH Computer Architecture News
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Figure 13 . 13 Power and Temperature Simulation Results
Table 1 . 1 Router component area * Maximum area in a single layer. k: buffer depth in flits per VC Area (µm2)
2DB
3DB
3DM*
3DM-E*
RC
1,717 ...
doi:10.1145/1394608.1382143
fatcat:i6pxabrnz5eklhykeijbknhsfi
Towards characterizing cloud backend workloads
2010
Performance Evaluation Review
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Our methodology for workload classification consists of: (1) identifying the workload dimensions; (2) constructing task classes using an off-the-shelf algorithm such as k-means; (3) determining the break ...
We applied k-means to the re-scaled data to calculate 18 task classes for each compute cluster. ...
We do this by using the workload dimensions as a feature vector and applying an off-the-shelf clustering algorithm such as k-means. ...
doi:10.1145/1773394.1773400
fatcat:u4vgpwfezjdkngkvdizebe6zfi
Coordinated power management of voltage islands in CMPs
2010
Performance Evaluation Review
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We chose the values of K P , K I and K D to be 0.4, 0.4 and 0.3, respectively, in all our evaluations such that the closed-loop poles of the transfer function lie within a unit-circle in the z-domain ( ...
These roots are called poles in control theory terminology and we use Matlab to determine the values of K P , K I and K D (P, I and D gains of the PID controller) such that the resulting system is always ...
doi:10.1145/1811099.1811086
fatcat:tcyzp6m4mjdihgbde2prvdvvja
Cache revive
2012
Proceedings of the 49th Annual Design Automation Conference on - DAC '12
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The relationship between retention time and thermal barrier is shown in Figure 3 , which can be modeled as t = C × e k∆ , where t is the retention time and ∆ is the thermal barrier, while C and k are ...
B T E b )ln( τ τ 0 )} (1) Jc,P S (τ ) = Jc0 + C τ γ (2) Jc,DR(τ ) = J c,T A (τ )+J c,P S (τ )e −k(τ −τc) 1+e −k(τ −τc) (3) where, J c,T A , J c,P S , J c,DR are the switching current densities for thermal ...
doi:10.1145/2228360.2228406
dblp:conf/dac/JogMXXNID12
fatcat:hoxi5tyemndh5jzk4esdqcpb4q
PEPON
2012
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12
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cores P k−2 caches P k−2 noc P erf k−3 P k−3 cores P k−3 caches P k−3 noc P F = P × A + ǫ, where P F = 0 B B @ P erf k P erf k−1 P erf k−2 P erf k−3 1 C C A , P = 0 B B @ P k cores P k caches P k noc ...
P k−1 cores P k−1 caches P k−1 noc P k−2 cores P k−2 caches P k−2 noc P k−3 cores P k−3 caches P k−3 noc 1 C C A , A = 0 @ a1 a2 a3 1 A , ǫ = 0 @ ǫ1 ǫ2 ǫ3 1 A . ...
doi:10.1145/2370816.2370828
dblp:conf/IEEEpact/SharifiMSKD12
fatcat:pg6buwmq6jaarmz7iz65jhwxqq
METE
2011
Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems - SIGMETRICS '11
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R 2 = 1 − P (ÎP Ci(k) − IP Ci(k)) 2 P (ÎP Ci(k) − IP Ci(avg)) 2 , (11) M AP E = 1 K K X k=1 |Î P Ci(k) − IP Ci(k) IP Ci(k) | . (12)
Dynamics of METE In this set of experimental results, we first show ...
Resource Broker 1 ref ) ( 1 k u 2 ref ) ( 2 k u ) ( 2 k u ) (k u n n ref ) ( 1 k u C1 C2 Cm L1 L1 L1 shared L2 cache to off chip memory ) ( k u n ) 1 ( − k IPC
System Model As mentioned earlier, a feedback ...
doi:10.1145/1993744.1993747
dblp:conf/sigmetrics/SharifiSMKD11
fatcat:xe6usil26na7rcpoefeaifxxay
Orchestrated scheduling and prefetching for GPGPUs
2013
SIGARCH Computer Architecture News
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A heterogeneous multiple network-on-chip design
2013
Proceedings of the 50th Annual Design Automation Conference on - DAC '13
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Asit Mishra asit.k.mishra@intel.com • App. has at least one outstanding packet • Processor is likely stalling → low IPC • App. has at least one outstanding packet • Processor is likely stalling → low ...
doi:10.1145/2463209.2488779
dblp:conf/dac/MishraMD13
fatcat:5pwwr6d6afadzjsg4vfcoudpty
Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs
[article]
2021
arXiv
pre-print
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(a) Input Sparsity with neuron indexing S C k ∈C = {x|x = 0, x ∈ [C k , H i , W j ], ∀(H i , W j ) ∈ H × W } Fig. ...
When working with a 3D tensor representation of feature maps, R C×H×W , through channel sparsity can be defined as the set: S HiWj ∈H×W = {x|x = 0, x ∈ [C k , H i , W j ] , ∀C k ∈ C} The notion of TC sparsity ...
arXiv:2109.07710v1
fatcat:apfd4gyddraj5cs3d66gtygsqm
Revealing genetic variation in local upland rice germplasm collection of Odisha
2017
Electronic Journal of Plant Breeding
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Wide array of genetic variation was observed for agro-economic traits among a set of 96 land races. Bhogi revealed short plant stature and it took just 78 days to mature. Khursudi and Asumakunda revealed high yield potential, while Salampikit, Kalakeri, Browngora, CR Dhan 40 and N22 were identified to have high degree of drought tolerance. Considering both leaf area and chlorophyll index; Kinari and Setka-1 had significantly higher value indicating efficient photosynthesis under water stress.
doi:10.5958/0975-928x.2017.00190.9
fatcat:4wh5zhlrpzdvvhxfn57cwe2kjy
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... lampikit and N 22 were identified to be nearly free from BLB (0.8-1.0 score) whereas, almost all other genotypes showed moderate to high susceptibility. High tillering capacity (Harisankar, CR Dhan 143-2-2, Kinari, Hiran, Badi and Kutiarasi), longer panicle (Kantadumer, Rasakadali , Damaraphuli, Padarabank, Somo , Asumakunda and Anjali), heavy panicle (Sarian, Dhobasaria, and Anjali), and more number of grains per panicle (Padarabank, Pustak and Pankopoat) were recorded in few landraces. Dhanisaria, Kanding and Dhubasaria recorded significantly higher percentage of grain fertility. Chinger-2 had very bold grains and popular upland varieties e.g., Khandagiri, Vanaprabha and Mandakini revealed higher grain and kernel length.
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
2008
2008 International Symposium on Computer Architecture
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Figure 13 . 13 Power and Temperature Simulation Results
Table 1 . 1 Router component area * Maximum area in a single layer. k: buffer depth in flits per VC Area (µm2)
2DB
3DB
3DM*
3DM-E*
RC
1,717 ...
doi:10.1109/isca.2008.13
dblp:conf/isca/ParkEDMXVD08
fatcat:cnkwp5pegjgu7juq4tgbykvj6q
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
2011
SIGARCH Computer Architecture News
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Emerging memory technologies such as STT-RAM, PCRAM and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-core architectures. This is due to the many attractive features these memory technologies posses: high density, low leakage, and non-volatility. However, the latency and energy overhead associated with the write operations of these emerging memories has become a major obstacle in their adoption. Previous works have
doi:10.1145/2024723.2000074
fatcat:7pyftbeswfgldp4f7wbbrvo4f4
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... d various circuit and architectural level solutions to mitigate the write overhead. In this paper, we study the integration of STT-RAM in a 3D multi-core environment and propose solutions at the on-chip network level to circumvent the write overhead problem in cache architecture with STT-RAM technology. Our scheme is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency. Thus, we prioritize cache accesses to the idle banks by delaying accesses to the STT-RAM cache banks that are currently serving long latency write requests. Through a detailed characterization of the cache access patterns of 42 applications, we propose an efficient mechanism to facilitate such delayed writes to cache banks by (a) accurately estimating the busy time of each cache bank through logical partitioning of the cache layer and (b) prioritizing packets in a router requesting accesses to idle banks. Evaluations on a 3D architecture, consisting of 64 cores and 64 STT-RAM cache banks, show that our proposed approach provides 14% average IPC improvement for multi-threaded benchmarks, 19% instruction throughput benefits for multi-programmed workloads, and 6% latency reduction compared to a recently proposed write buffering mechanism.
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