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Very large scale integration
1982
Microprocessing and Microprogramming
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However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. ...
Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. ...
This trade off is becoming more and more demanding in sub-100 nm technologies; because, as technology scales, leakage current of transistors increases tremendously which means that wide dynamic gates require ...
doi:10.1016/0165-6074(82)90110-7
fatcat:6crac76ewraddo3ydimu4dhdyq
Very large scale integration 1983
1984
Microprocessing and Microprogramming
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However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. ...
Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. ...
This trade off is becoming more and more demanding in sub-100 nm technologies; because, as technology scales, leakage current of transistors increases tremendously which means that wide dynamic gates require ...
doi:10.1016/0165-6074(84)90074-7
fatcat:jrucijtd5nbwjcnmablbef3kci
Emerging technologies and nanoscale computing fabrics
2009
2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)
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Further, significant technological advances have been made recently to achieve 95-98% horizontally aligned semiconducting CNTs [9] and, separately, hybrid integration with CMOS [10] . ...
on very flexible hardware. ...
doi:10.1109/vlsisoc.2009.6041320
fatcat:xcotcekxwfho5abh6ydylfc564
Unified functional decomposition via encoding for FPGA technology mapping
2001
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper we propose a novel method to unify functional single-output and multiple-output decomposition. ...
Functional decomposition has recently been adopted for look-up tabel (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. ...
Fortunately, our encoding method is suitable for hyperfunctions, which are combined from small functions and eventually could be large. The overall technology mapping is promising. ...
doi:10.1109/92.924031
fatcat:sq5jrtgcevadhbjrhih36ql7ti
Microfluidic very large scale integration (mVLSI) with integrated micromechanical valves
2012
Lab on a Chip
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Because the density increase is greater than two orders of magnitude, we describe this technology as microfluidic very large scale integration (mVLSI), analogous to its electronic counterpart. ...
We have shown that these valves can be fabricated at densities approaching 1 million valves per cm 2 , substantially exceeding the current state of the art of microfluidic large-scale integration (mLSI ...
Fig. 1 1 (a) Intermediate fabrication steps (top) and cross section (bottom) of the three-layer design for microfluidic very large scale integration. ...
doi:10.1039/c2lc40258k
pmid:22714259
fatcat:iybrb6e5j5b2di4dswkvy4sno4
Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design
2015
2015 20th IEEE European Test Symposium (ETS)
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By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, "microfluidic Very Large-Scale Integration" (mVLSI). ...
This paper presents the state-of-the-art in the mVLSI platforms and emerging research challenges in the area of continuous-flow microfluidics, focusing on testing techniques and fault-tolerant design. ...
The technology is therefore referred to as "microfluidic Very Large-Scale Integration" (mVLSI) [4] . ...
doi:10.1109/ets.2015.7138736
dblp:conf/ets/AraciPC15
fatcat:miiiy4b2f5bjjo3ljgohciuyue
Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology
1997
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The CPU chip integrates 92 340 transistors on a 7 2 7 mm 2 die and dissipates 6.13 W at 180 MHz. ...
We have been able to verify novel GaAs SBFL standard cells and compare measured CPU performance with performance estimates based on circuit and device models. ...
Cappon, and J. Toole, whose appreciation of this work made its completion possible. Testing of F-RISC/I was made possible through the use of equipment at IBM. ...
doi:10.1109/92.585228
fatcat:rltlxvfphngl7bvlef7gvwhj3a
A process-tolerant cache architecture for improved yield in nanoscale technologies
2005
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. ...
Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. ...
State-of-the-art microprocessor designs devote a large fraction of the chip area to memory structures, e.g., multiple levels of instruction and data caches, translation look-aside buffers, and prediction ...
doi:10.1109/tvlsi.2004.840407
fatcat:ghjhjs5zrrcsjpamdked5zzwtq
High-purity Refractory Metals for Thin Film Metallization of VLSI
[chapter]
2018
Very-Large-Scale Integration
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The study reveals the possibilities and conditions of depositing the silicides and titaniumtungsten barrier layers by both the laser evaporation and magnetron sputtering. ...
levitation, EB floating zone melting, EB melting, and electric arc vacuum melting as well as chemical purifying by ion exchange and halides. ...
Very-Large-Scale Integration used for a production of targets, on the specific resistivity of thin refractory metal films, there are sputtered targets produced both by the standard PM procedure and EB ...
doi:10.5772/intechopen.69126
fatcat:lrv3gf3glzhrjfyarjhuguw4by
Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories
[article]
2019
arXiv
pre-print
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We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction ...
Arrays of Vortex Transitional (VT) memory cells with functional density up to 1 Mbit/cm^2 have been designed, fabricated, and successfully demonstrated. ...
We are grateful to Vladimir Bolkhovsky and Scott Zarr for their part in high-Jc process development and running the process used in this work. ...
arXiv:1902.08302v1
fatcat:ibz73ktakzdzjiwodcqskda4jy
Guest editorial: System-level interconnect prediction
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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A S in the past two special sections of the IEEE TRANSACTIONS oN VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS on system-level interconnect prediction (SLIP) (in the December issues of 2000 and 2001), there ...
In conclusion, the papers gathered within this special section represent the state-of-the-art in SLIP, provided by leading researchers from both academia and industry. ...
A S in the past two special sections of the IEEE TRANSACTIONS oN VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS on system-level interconnect prediction (SLIP) (in the December issues of 2000 and 2001) , ...
doi:10.1109/tvlsi.2003.810753
fatcat:rvjitcxuu5dxfajthnrqwegc2y
Guest Editorial System-Level Interconnect Prediction
2007
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In state-of-the-art FPGAs, a very large amount of interconnect resources are available anyway. ...
Driven by the limitations of electrical interconnect, the quest for alternative interconnect technologies is also very active and reflected in recent SLIP programs. ...
doi:10.1109/tvlsi.2007.900756
fatcat:cjrhpal5mvhunfsj64rkyiaakm
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
2016
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Technology scaling has enabled fast increase in the number of cores integrated in many-core systems. ...
Although that scheme can achieve the optimal temperature reduction, however, it faces severe computation bottleneck and communication congestion when the many-core processors evolve to large-scale with ...
INTRODUCTION Technology scaling has enabled a trend in which the number of cores integrated inside one chip grows rapidly [1] . ...
doi:10.1109/tvlsi.2015.2497469
fatcat:zf3hnrzetng33j6jhiqdfl7b2u
Optimization of scannable latches for low energy
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. ...
This paper covers a range of issues in the design of latches and flip-flops for low-power applications. ...
Meltzer and S. Kosonocky for useful discussions; G. Gristede and A. Haen for the design flow support; and K. Warren and J. Moreno for the management support. ...
doi:10.1109/tvlsi.2003.814322
fatcat:4v2734jst5danifhpfgy423i6e
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies
2011
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. ...
Index Terms-3-D integrated circuit (IC), 3-D integration, coaxial through-silicon via (TSV), power delivery, power grid, TSV. ...
We begin in Section II with relevant background information on 3-D integration technology and a review of the state of the art in 3-D power delivery modeling and analysis. ...
doi:10.1109/tvlsi.2009.2038165
fatcat:j7pavtsc7raxdihayjkoq6i4sy
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