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Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Mohammad Khan, Abdul Ansari
2012 Open Computer Science  
In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder.  ...  AbstractThe Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications.  ...  Future work includes research on the effect of different other arbitration policies on latency, and the quality of service parameter for inter-layer communication in 3-D Network-on-Chip.  ... 
doi:10.2478/s13537-012-0006-8 fatcat:2nu3p7j3trharlh4rq7wk4epye

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Doaa A. Hamdi, Samy Ghoniemy, Yasser Dakroury, Mohammed A. Sobh
2021 IEEE Access  
In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented.  ...  While the power consumption is reduced by 76.5% and 78.5% for the 4 × 4 and 8 × 8 network structures, respectively. Besides, the chip area is reduced by 33.4%.  ...  THE PROPOSED SOFTWARE DEFINED CONTROLLER FOR PHOTONIC NETWORK ON CHIP Software-Defined Networking (SDN) refers to a new approach for network programmability, that is, the capacity to initialize, control  ... 
doi:10.1109/access.2021.3058238 fatcat:houzvoxstzdkpmmmux4sapk2ku

μBrain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

Jan Stuijt, Manolis Sifalakis, Amirreza Yousefzadeh, Federico Corradi
2021 Frontiers in Neuroscience  
For these reasons, μBrain is ultra-low-power and offers software-to-hardware fidelity. μBrain enables always-on neuromorphic computing in IoT sensor nodes that require running on battery power for years  ...  We present an instantiation of the μBrain architecture in a 40 nm CMOS digital chip and demonstrate its efficiency in a radar-based gesture classification with a power consumption of 70 μW and energy consumption  ...  It is less efficient for implementing very deep neural networks as silicon area efficiency plays an essential role. The lack of time-multiplexed neuron cores in µBrain limits the scalability.  ... 
doi:10.3389/fnins.2021.664208 pmid:34093116 pmcid:PMC8170091 fatcat:edo2oa6xc5ba5jjtdzhhz5c244

Physical Unclonable Functions (PUF) for IoT Devices [article]

Abdulaziz Al-Meer, Saif Al-Kuwari
2022 arXiv   pre-print
In this survey we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.  ...  It provides less cost of computational resources which prevent high power consumption and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (  ...  Acknowledgments This work is partially funded by the G5797 "Developing Physical-Layer Security Schemes for Internet of Things Networks" project under the NATO's Science for Peace Programme.  ... 
arXiv:2205.08587v1 fatcat:ytp7ot6pc5asbi46qxsdeewg2u

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Domer, Daniel D. Gajski
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures.  ...  At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components.  ...  In [21] - [23] , the network-on-chip (NoC) approach is proposed.  ... 
doi:10.1109/tcad.2007.895794 fatcat:cqrbgqnhurfzremouexfn5jwmu

A low area and low power programmable baseband processor architecture

E. Tell, A. Nilsson, D. Liu
2005 Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)  
A demonstrator chip for 802.11a/b/g physical layer baseband processing was manufactured in 0.18 µm CMOS. The silicon area is 2.9 mm 2 , including all memories.  ...  A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a configurable network.  ...  An 802.11a/b/g baseband processor demonstrator chip, with accelerators for ADC/DAC inter-face+frontend processing, demapping, interleaving, scrambling, CRC, Walsh transform, and MAC-layer interface was  ... 
doi:10.1109/iwsoc.2005.14 dblp:conf/iwsoc/TellNL05 fatcat:j5bfbspsejc2lpnuh4sqhigdza

NOC'S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

Sujata. S.B
2020 International Journal of Advanced Trends in Computer Science and Engineering  
To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia  ...  As per requirements at present situation for better communication within core networks, this paper mainly focused on commonly used architectures and their inter components connectivity's that can deal  ...  We analyzed both 64-thread and 128-thread systems, and our proposed method demonstrates the important developments in system performance.  ... 
doi:10.30534/ijatcse/2020/240932020 fatcat:kj4yllfklffqrjuaipr2c26jyy

On-FPGA Communication Architectures and Design Factors

Terrence T. Mak, Pete Sedcole, Peter K. Cheung, Wayne Luk
2006 2006 International Conference on Field Programmable Logic and Applications  
These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication.  ...  The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing  ...  In [34] , a dynamic network on chip (DyNoC) for coarse-grain programmable fabrics was proposed. It is an extension of an 1-D shared bus architecture to a 2-D network interconnect architecture.  ... 
doi:10.1109/fpl.2006.311209 dblp:conf/fpl/MakSCL06 fatcat:xmwjluwdpva4bnm2abhitvtvce

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
Metal layers TSV (Through-Silicon-Via) C4 Pad Microbump 1 These two tables are based on IBM 65nm technology for high performance microprocessor design 3 Benefits of 3D Integrated Circuits The following  ...  The emerging three-dimensional (3D) integration technology is one of the promising solutions to overcome the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements  ...  for Down, along with the C arbiters and Switch Arbiters), and is architecture a 3D Symmetric NoC, yer movement bear identical characal, as illustrated in Figure 3 : 3 A 3D Symmetric NoC Network during  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

Energy-Efficient System-Level Design [chapter]

Luca Benini, Giovanni De Micheli
2002 Power Aware Design Methodologies  
channel as well as system and application software onto a single chip.  ...  Moving from a set of case studies, we give an overview of energy-efficient systemlevel design, emphasizing a component-based approach.  ...  Future high-performance shared-medium on-chip micro-networks may evolve in the same direction as high-speed local area networks, where contention for a shared communication channel can cause errors, because  ... 
doi:10.1007/0-306-48139-1_16 fatcat:rikxlmoqmjfd3o3whfmbnvymwm

Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets

C. Zamarreno-Ramos, A. Linares-Barranco, T. Serrano-Gotarredona, B. Linares-Barranco
2013 IEEE Transactions on Biomedical Circuits and Systems  
Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance.  ...  One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 × 10 3 neurons and almost 32 million synapses.  ...  The high-speed available for digital inter-chip communications is exploited in AER to timemultiplex numerous synaptic connections between neurons, which only need to be active during a spike (also called  ... 
doi:10.1109/tbcas.2012.2195725 pmid:23853282 fatcat:qzaghkudjja6joa3cy4rbnlxvu

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

J.Y. Hur, T. Stefanov, S. Wong, K. Goossens
2012 IET Computers & Digital Techniques  
Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs).  ...  Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping.  ...  of the on-chip networks.  ... 
doi:10.1049/iet-cdt.2010.0105 fatcat:42oxxsfupbe4joyddqkd4qhyt4

Set-based Obfuscation for Strong PUFs against Machine Learning Attacks [article]

Jiliang Zhang, Chaoqun Shen
2019 arXiv   pre-print
Experimental results show that for a 64x64 Arbiter PUF, when the size of set is 32 and even if 1 million CRPs are collected by attackers, the prediction accuracies of Logistic regression, support vector  ...  In order to address these issues, we propose a Random Set-based Obfuscation (RSO) for Strong PUFs to resist machine learning attacks.  ...  The whole authentication process on the server side is shown in Fig. 3 . 1) Enrollment phase: For a Device i , the device identifier id i is stored on the one-time programmable storage (OPT-S) through  ... 
arXiv:1806.02011v4 fatcat:rclgs6eozzhbxky7fzwqhkf4ui

Exploring programming model-driven QoS support for NoC-based platforms

Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli
2010 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10  
Networks-on-Chip (NoCs) are being increasingly considered as a central enabling technology to communication-centric designs as more and more IP blocks are integrated on the same SoC.  ...  The complex and non-uniform nature of network traffic generated by parallel applications running on a large number of possibly heterogeneous IPs makes a strong case for providing Quality of Service (QoS  ...  Acknowledgments This work was partially supported through AGAUR (Ref. 2009BE200202), ITEA2 ParMA project, as well as, JTI SMECY and FP7 SHARE and PRO3D projects funded by the European Community.  ... 
doi:10.1145/1878961.1878977 dblp:conf/codes/JovenMABM10 fatcat:bx7iq5co35bk7btcsslrptst64

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007 Proceedings of the International Conference on Parallel Processing  
In this paper, we propose a class of 3-D topologies called Xbar-connected Network-on-Tiers (XNoTs), which consist of multiple network layers tightly connected via crossbar switches.  ...  Path sets at the bottom layer close to the heat sink of the chip can be selectively employed in order to mitigate the heat-dissipation problem of 3-D ICs.  ...  Network Logic Area The network logic area in a 3-D NoC is composed of routers, network interfaces, and vertical links.  ... 
doi:10.1109/icpp.2007.79 dblp:conf/icpp/MatsutaniKA07 fatcat:mpqhgbl7lrdjjmbvwhfj3idp7a
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