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Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors

A. Hodjat, I. Verbauwhede
2006 IEEE transactions on computers  
With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18-m CMOS technology.  ...  Therefore, the over 30 Gbits/s, fully pipelined AES processor operating in the counter mode of operation can be used for the encryption of data on optical links.  ...  Area efficient architectures for fully pipelined high speed AES processors that can provide an encryption throughput of 30 to 70 Gbits/s for a 0.18-m CMOS ASIC technology are presented.  ... 
doi:10.1109/tc.2006.49 fatcat:c4yw42hek5acbp25y2e4zrtg74

Minimum area cost for a 30 to 70 Gbits/s AES processor

A. Hodjat, I. Verbauwhede
IEEE Computer Society Annual Symposium on VLSI  
This paper presents the design decisions and area optimizations to obtain a high throughput, over 30 Gbits/s AES processor.  ...  With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18 ÿm CMOS technology.  ...  The authors would like to acknowledge Professor Miodrag Potkonjak for his feedback in this project.  ... 
doi:10.1109/isvlsi.2004.1339512 dblp:conf/isvlsi/HodjatV04 fatcat:mmis7narjrhypgw25dmzh4hmqy

Implementation of AES-GCM encryption algorithm for high performance and low power architecture Using FPGA
English

2014 International Journal of Research and Applications  
Galois Hash is used for authentication, and the Advanced Encryption Standard (AES) block cipher is used for encryption in counter mode of operation.  ...  The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data.  ...  This paper presents the area-throughput trade-offs of a fully pipelined, ultra high speed AES encryption processor.  ... 
doi:10.17812/ijra.1.3(26)2014 fatcat:i7byhqbchbdfdabncy3dje4d54

DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

Saar Drimer, Tim Güneysu, Christof Paar
2008 2008 16th International Symposium on Field-Programmable Custom Computing Machines  
Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput.  ...  This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs.  ...  Acknowledgments We thank Xilinx for the donation of development tools, and David Ellington for helping resolve simulation issues. Saar Drimer's research is funded by Xilinx Inc.  ... 
doi:10.1109/fccm.2008.42 dblp:conf/fccm/DrimerGP08 fatcat:gngmxhyfkndlploq4owkvkbunm

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2017 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
stored or sent over the network at various stages of the analytics pipeline.  ...  Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues.  ...  This parameter supports a trade-off between security and throughput.  ... 
doi:10.1109/tcsi.2017.2698019 fatcat:x5o4ec64gnbirpxyqvor2swi7a

Improving Memory Encryption Performance in Secure Processors

Jun Yang, Lan Gao, Youtao Zhang
2005 IEEE transactions on computers  
We performed experiments to study the trade-off between storage size and performance penalty.  ...  For stand-alone computers, a key observation is that, other than the processor, any component is vulnerable to security attacks.  ...  In [13] , the implementation of a 128-bit AES unit can achieve 30 $ 70 Gbit/s with 175 $ 380K gates using 0.18m CMOS technology.  ... 
doi:10.1109/tc.2005.80 fatcat:n5npyyer3zdm3omvztwnk2gszy

Future trends in microelectronics - reflections on the road to nanotechnology

1997 Precision engineering  
Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining  ...  Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for  ...  The authors would like to thank the following people for both technical assistance and critical comments: Rolf Landauer, John Heidenreich, J. Frank White, John Hummel, Steve Greco, C.-K.  ... 
doi:10.1016/0141-6359(97)90048-9 fatcat:j7blw4wn6zbitmoqqffj46g54e

DLL architecture for OFDM based VLC transceivers in FPGA

Luis Duarte, Luis Rodrigues, Luis N. Alves, Carlos Ribeiro, Monica Figueiredo
2016 2016 10th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP)  
The main objective of this dissertation work is to implement an efficient DLL in a Microblaze soft processor in a FPGA and to study its usage in a broadcast VLC system for lighting systems.  ...  Therefore, the twenty-first century is marked by a growing demand for bandwidth in wireless communications, as it allows users to communicate and access daily applications even from remote areas.  ...  Recently, in 2015, Fraunhofer HHI developed a VLC demonstrator that exploits a much higher bandwidth of up to 180 MHz and achieves a transmission rate in laboratory experiments of over 1 Gbit/s per single  ... 
doi:10.1109/csndsp.2016.7573949 dblp:conf/csndsp/DuarteRARF16 fatcat:mudtujqt2bdhbgva5h7ruddjku

Mobile Private Contact Discovery at Scale

Daniel Kales, Christian Rechberger, Thomas Schneider, Matthias Senker, Christian Weinert
2019 USENIX Security Symposium  
Concretely, we present novel precomputation techniques for correlated oblivious transfers (reducing the online communication by factor 2x), Cuckoo filter compression (with a compression ratio of ≈ 70 %  ...  In a protocol performing oblivious PRF evaluations via garbled circuits, we replace AES as the evaluated PRF with a variant of LowMC (Albrecht et al., EUROCRYPT'15) for which we determine optimal parameters  ...  Acknowledgments This work was co-funded by the DFG as part of project E4 within the CRC 1119 CROSSING and project A.1 within the RTG 2050 "Privacy and Trust for Mobile Users", by the BMBF and the HMWK  ... 
dblp:conf/uss/KalesR0SW19 fatcat:ey2gfxl4czfyvasafzxz7waqdu

MULTI-PROCESSOR SYSTEMS-ON-CHIP WITH CONFIGURABLE HARDWARE ACCELERATION

Davide Rossi
unpublished
Gbit/s bandwidth.  ...  trade-off for each application.  ... 
fatcat:kbbmdx6ohnghbbggobftitateu

High Performance Propagation Of Large Object Populations In Earth Orbits

Marek Möckel, Enrico Stoll, Kefei Zhang
2016 Zenodo  
This reduces the overall run time for large object populations from hours to minutes.  ...  It was programmed to run on graphics processing units (GPUs), hardware designed for massively parallel execution of up to thousands of concurrent threads.  ...  For any given problem, a trade-off must be found that is both sufficiently accurate and sufficiently fast.  ... 
doi:10.5281/zenodo.48180 fatcat:5amzzse5prg7hmrp6647m7gvpi

Mapping and management of communication services on MP-SoC platforms [article]

Marescaux, TM (Théodore), Corporaal, H (Henk), Verkest, DTML (Diederik)
2007
The aggregated bandwidth of a 32 ports SPIN network (16 routers) is over 100 Gbit/s for a total area of 4.6 mm 2 (0.25 mm 2 per router) [14] .  ...  The total router area is 0.175mm 2 . The bandwidth per port provided by the router reaches 16 Gbit/s. The area of the network interface is 0.172 mm 2 in 0.13 μm technology.  ...  can be time-annotated to model any type of processor).  ... 
doi:10.6100/ir629360 fatcat:e5kz6vvr7fguldjhdpjyge3u34

Real-Time Trace Decoding and Monitoring for Safety and Security in Embedded Systems

Augusto Wankler Hoppe, Jürgen Becker, Fernanda Kastensmidt
2022
I want to give my gratitude to Prof. Becker for welcoming me to Karlsruhe and ITIV.  ...  To my D&D group, Nidhi, Simon, Gabriela, Florian, and Tim. To Steffen for geeking out with me about films and games. To my colleagues at the PES lab.  ...  However, this approach creates a considerable bandwidth as each completed instruction generates 128-bit data packets, 1.6 Gbit/s for a processor running at 100 MHz.  ... 
doi:10.5445/ir/1000148789 fatcat:ldulycy3yzegzaqayrcp5xhwdq

Energy-efficient design of an asynchronous network-on-chip

Daniel J. Gebhardt
2012
It studies link pipelining techniques that yield improved throughput in an energy-efficient manner.  ...  Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation.  ...  ACKNOWLEDGEMENTS I am grateful for the diverse experiences I have had at the University of Utah, from computer architecture and network research to seminars on data visualization and computational biochemistry  ... 
doi:10.26053/0h-gg22-f000 fatcat:iu6juy34yjghnp537bolatj2oe

An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks

Jaco Hofmann
2019
Compared to commodity solutions using CPUs and GPUs, FPGAs are more expensive and more time consuming to develop for.  ...  Nonetheless, FPGAs also offer an opportunity to develop faster accelerators with a smaller energy envelop for rapidly changing applications.  ...  Figure 8 .12 shows the bandwidth per node necessary to match the baseline running at 5 Gbit/s. To achieve the same performance using a 5 000 000 000 tuple A relation only 2.347 Gbit/s are necessary.  ... 
doi:10.25534/tuprints-00010355 fatcat:4567mf3vvjbvxilumnmkbmqwgu
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