8,731 Hits in 7.0 sec

Sub-wavelength Lithography and Variability Aware SRAM Characterization

P. Dobrovolny, M. Miranda, P. Zuber
2012 Radioengineering  
Litho process variations correspond to random changes in the actual optical conditions (dose and focus) which develop at every mask exposure, hence from die to die.  ...  In contrast to this, the intrinsic variability of the devices and interconnects originating mostly from local Random Dopant Fluctuations (RDF) and Line Edge Roughness (LER) has a purely spatially uncorrelated  ...  The estimated yield loss can be of parametric nature (i.e., failure of the memory access to meet the target cycle time or insufficient read margin for successful operation or similar); but it can be of  ... 
doaj:49a963f883ce435cbfabd46eb5005fe8 fatcat:qll3ixy6xzfkvbz6orqdjn4fne


Mark Gottscho, Abbas BanaiyanMofrad, Nikil Dutt, Alex Nicolau, Puneet Gupta
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising approach to improve energy efficiency of memories in the presence of nanoscale process variation.  ...  This architecture achieves lower static power for all effective cache capacities than a recent more complex FTVS scheme.  ...  Modeling Cache Fault Behavior Probabilistic failure models were used to analytically compare power/capacity tradeoffs, predict yield, and guide the generation of random fault map instances for the simulation  ... 
doi:10.1145/2792982 fatcat:wswxryw3nzehtahpdd5vlmuj2e

Integrated software tools for the memory management of low-energy embedded signal processing systems

Florin Balasa, Dhiraj K. Pradhan
2012 2012 5th International Congress on Image and Signal Processing  
This paper presents an energy-aware CAD methodology for the system-level exploration of hierarchical storage organizations, focusing mainly on data-intensive signal processing applications.  ...  The last phase of the methodology is a novel approach for powerefficient banking of the on-chip memory. keywords-Memory management, memory allocation, embedded signal processing systems, signal-to-memory  ...  This SoC consumes 240 mW at 60 M Hz, and the memory access power -to embedded static random-access memory (SRAM) buffers, to various caches, and to the dynamic random-access memory (DRAM) -is the dominant  ... 
doi:10.1109/cisp.2012.6469819 fatcat:mdsdpatifre3vf53ulwfu4usuu

Architectural Leakage-Aware Management of Partitioned Scratchpad Memories

Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
We show that the total energy (dynamic and static) cost function yields a non-convex partitioning space, making smart exploration the only viable option; we propose an effective randomized search in the  ...  MEMORY ENERGY CHARACTERIZA-TION Memory Energy Model Key to our method is the availability of a low-leakage sleep state for a given memory block.  ...  For this reasons, several leakage-aware memories structures, in particular for caches, have been devised in the recent past ( [11] - [16] ).  ... 
doi:10.1109/date.2007.364541 fatcat:qaiiagvh2vawjhc3wsd6nginpa

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

S. Mukhopadhyay, H. Mahmoodi, K. Roy
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations  ...  The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.  ...  Hence, the cell configurations and the memory architecture can be optimized for maximizing memory yield.  ... 
doi:10.1109/tcad.2005.852295 fatcat:hfum4gi6nrgs7ko2mqwj63bg3y

Notice of Violation of IEEE Publication Principles A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

Arghavan Asad, Salman Onsori, Mahmood Fathy, Mohammad Reza Jahed-Motlagh, Kaamran Raahemifar
2016 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)  
For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system.  ...  In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies.  ...  Dynamic energy consumption per read and write access by the STT-RAM memory bank Static power consumed by each SRAM memory bank at maximum temperature limit Static power consumed by each STT-RAM  ... 
doi:10.1109/ccece.2016.7726817 dblp:conf/ccece/AsadOFMR16 fatcat:ej36y4vsi5e6zimwdh5dmirohe

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

Jeren Samandari-Rad, Matthew Guthaus, Richard Hughey
2014 IEEE Access  
In this paper, we develop methods for robust and resilient six-transistor-cell static random access memory (6T-SRAM) designs that mitigate the effects of device and circuit parameter variations.  ...  Our goal in combining modeling techniques is to help minimize all major types of variability and to consequently predict and optimize speed and yield for the next generation 6T-SRAMs.  ...  The six-transistor-cell static random access memory (6T-SRAM) ( Fig. 1) is the conventional choice for most on-chip memory designs.  ... 
doi:10.1109/access.2014.2323233 fatcat:hsqprvcb2zhalegj2gtletna7e

Variability aware modeling for yield enhancement of SRAM and logic

M Miranda, P Zuber, P Dobrovolny, P Roussel
2011 2011 Design, Automation & Test in Europe  
On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability.  ...  This paper summarizes the challenges for statistical characterization of SRAM and logic.  ...  The authors acknowledge the contribution of Lucas Brusamarello on the experiments carried out in this work.  ... 
doi:10.1109/date.2011.5763193 dblp:conf/date/MirandaZDR11 fatcat:q7jp4ddzhrglxahkkt5l342eya

A Review on Security in Cache Memories

R. Vijay Sai, S. Saravanan
2016 Indian Journal of Science and Technology  
Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations.  ...  Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested  ...  Reliability of cache memories [17] [18] [19] using identical tag bits, reduction of power and cell stability based on dynamic isolated read static random success memory and data scrambling based secured  ... 
doi:10.17485/ijst/2016/v9i48/96037 fatcat:vv5p5sksczacdp35bndfpd6o3a

Accelerating Database Systems Using FPGAs: A Survey

Philippos Papaphilippou, Wayne Luk
2018 2018 28th International Conference on Field Programmable Logic and Applications (FPL)  
This survey presents a systematic review of research relating to accelerating analytical database systems using FPGAs.  ...  The review includes studies of database acceleration frameworks and accelerator implementations for various database operators.  ...  The authors would like to thank Chris Brooks and Rosie Prior from dunnhumby for their valuable involvement in the partnership program.  ... 
doi:10.1109/fpl.2018.00030 dblp:conf/fpl/PapaphilippouL18 fatcat:gcnfescocngjbkdysdzj3rhpvy

Yield-Aware Cache Architectures

Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
To attack this growing problem, we develop four yield-aware microarchitecture schemes for data caches. The first one is called Yield-Aware Power-Down (YAPD).  ...  A third approach targets delay violation in data caches. Particularly, we develop a VAriable-latency Cache Architecture (VACA).  ...  Section 3 illustrates our cache architecture and our methodology for modeling the process variations on it. Section 4 describes our yield-aware architectures.  ... 
doi:10.1109/micro.2006.52 dblp:conf/micro/OzdemirSMAZ06 fatcat:5wehfjo5ivbjncni2zxvgrrnri

Data-centric execution of speculative parallel programs

Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel Emer, Daniel Sanchez
2016 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)  
tasks likely to conflict, and (iii) balancing tasks across tiles in a locality-aware fashion.  ...  We design simple hardware techniques that allow a state-of-the-art, tiled speculative architecture to exploit hints by: (i) running tasks likely to access the same data on the same tile, (ii) serializing  ...  This work was supported in part by C-FAR, one of six SRC STARnet centers by MARCO and DARPA, and by NSF grants CAREER-1452994 and CCF-1318384.  ... 
doi:10.1109/micro.2016.7783708 dblp:conf/micro/JeffreySAES16 fatcat:b6nbzdafhzcazp74ify77niwa4

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
In this paper, we extend our previously proposed hybrid analyticalempirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to  ...  Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs.  ...  OVERVIEW OF OUR MODEL A. SRAM The six-transistor-cell static random access memory (6T-SRAM) ( Fig. 1) is the conventional choice for most onchip memory designs.  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-chip Cache

Balaji Vaidyanathan, Yu Wang, Yuan Xie
2009 2009 IEEE International Workshop on Memory Technology, Design, and Testing  
However, the poor scaling trend associated with devices still remains as a challenge in realizing large on-chip memories.  ...  Technology scaling is increasingly yielding diminishing returns in terms of product performance, power, and its yield.  ...  [3] demonstrated 3D Static Random Access Memory (SRAM) architecture that could reduce the SRAM access delay by 1.8x and the active power consumption by 3.4x due to the decreased bit-line capacitance  ... 
doi:10.1109/mtdt.2009.21 fatcat:p4ykkrfyaffuvpkurzlvgtobwi

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

Arghavan Asad, Ozcan Ozturk, Mahmood Fathy, Mohammad Reza Jahed-Motlagh
2017 Microprocessors and microsystems  
In the proposed architecture, for future chip-multiprocessors (CMPs), we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon.  ...  Also, for the first time, we propose a detailed power model which is useful for future dark silicon CMPs power modeling.  ...  The model can be very useful for future dark silicon aware power modeling in many core systems. Table 3 lists the parameters used in this model.  ... 
doi:10.1016/j.micpro.2017.03.011 fatcat:f5mn5xmyxbeevjcaa4h7b26cdq
« Previous Showing results 1 — 15 out of 8,731 results