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Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

R. Venkata, W. Wong, T. Tran, V. Chan, T. Hoang, H. Lui, B. Ton, S. Shumurayev, Chong Lee, Shoujun Wang, Huy Ngo, M. Kabani (+10 others)
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.  
Another challenge described, is the implementation of 39 source-synchronous channels at 100Mbps to 1Gbps, utilizing Dynamic Phase Alignment (DPA).  ...  The SoPC (System on a Programmable Chip) aspects of the Stratix GX™ FPGA with 3.125Gbps SERDES are described. The FPGA was fabricated on a 0.13um, 9-layer metal process.  ...  Acknowledgements The author would like to thank the members of the Altera development teams -Layout, CAD, Product Engineering, Software, Applications, and Product Planning -whose valuable contributions  ... 
doi:10.1109/cicc.2003.1249481 fatcat:ymeierdzxfcknp3gy4njzlkupu