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Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations

Mark Hempstead, Gu-Yeon Wei, David Brooks
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
This work investigates tradeoffs between leakage and active power for low-throughput applications.  ...  We study these issues across a range of process technologies on a computing architecture that provides explicit support for fine-grain leakage-control techniques such as Vdd-gating and adaptive body bias  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSF, Intel or IBM.  ... 
doi:10.1145/1176760.1176805 dblp:conf/cases/HempsteadWB06 fatcat:d4m4q4dgszcklhprbcm5ftgi2q

Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications

Evgeni Krimer, Robert Pawlowski, Mattan Erez, Patrick Chiang
2010 IEEE computer architecture letters  
While Moore's law scaling continues to double transistor density every technology generation, supply voltage reduction has essentially stopped, increasing both power density and total energy consumed in  ...  In this paper, we propose a near energy-optimal, stream processor family that relies on massively parallel, near-threshold VLSI circuits and interconnect, incorporating cooperative circuit/architecture  ...  INTRODUCTION P ROCESSORS at all market segments are increasingly power and energy-constrained.  ... 
doi:10.1109/l-ca.2010.5 fatcat:sxyvizz5kbcrvgf3cu5zz5ip7y

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS

Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester
2012 IEEE Journal of Solid-State Circuits  
The second technique introduces a parallel-pipelined architecture that suppresses leakage energy by ensuring full utilization of functional units and reduces memory size.  ...  energy efficiency of the circuit.  ...  We use such an FFT core as a demonstration vehicle for several circuit and architectural techniques aimed at reducing and , while achieving unusually high throughput for a subthreshold circuit.  ... 
doi:10.1109/jssc.2011.2169311 fatcat:b6dmqcr5cjhqfd3lhtv5lhbqym

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
Finally, we present design challenges and future research directions for HPEEC system development.  ...  This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting  ...  ACKNOWLEDGMENTS This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the US National Science Foundation (NSF) (CNS-0953447 and CNS-0905308).  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors

SukHwan Lim, Yong Pan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang
2021 2021 IEEE International Solid- State Circuits Conference (ISSCC)  
The fourth talk explores the co-design of hardware and DNN models to achieve stateof-the-art performance for real-time, extremely energy/throughput-constrained inference applications.  ...  Performance scaling and power efficiency with traditional computing architectures becomes increasingly challenging as next-generation technology nodes provide diminishing performance and energy benefits  ...  The holistic co-design across algorithm, circuit, and device levels emerges more importantly for execution acceleration, energy efficiency, and design flexibility.  ... 
doi:10.1109/isscc42613.2021.9365804 fatcat:6qgx72c6bjcgndua43f4fsdggm

Design in the Power-Limited Scaling Regime

Borivoje Nikolic
2008 IEEE Transactions on Electron Devices  
Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings.  ...  This paper examines technology options in the power-limitedscaling regime and reviews sensitivity-based analysis that can be used for the optimal selection of optimal architectures and circuit implementations  ...  Horowitz and R. Brodersen, for the sensitivity-based optimization.  ... 
doi:10.1109/ted.2007.911350 fatcat:cnrkl4oxk5h6rfrlfadwl75agu

A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS

Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, D. Blaauw, D. Sylvester
2013 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers  
Hence, there is a need for high performance and energy-efficient feature extraction for use in emerging mobile applications.  ...  However, high-quality feature extraction algorithms require high performance and power-hungry processing, making them unsuitable for power-constrained embedded systems unless their scope is restricted  ...  Acknowledgements: Funding support by the Army Research Laboratory, IC fabrication support of STMicroelectronics and test support of Nathan Michael and Shaojie Shen at the University of Pennsylvania are  ... 
doi:10.1109/isscc.2013.6487684 dblp:conf/isscc/JeonKLZBS13 fatcat:wtmujdkyingkppjmdzdaawsufa

Technologies for Ultradynamic Voltage Scaling

A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N. Verma
2010 Proceedings of the IEEE  
Circuits such as logic cells, static random access memories, analog-digital converters and dc-dc converters can be used as building blocks for applications that can function efficiently over a wide range  ...  This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted.  ...  Acknowledgment The authors would like to acknowledge Dimitri Antoniadis, Yu Cao, Eric Wang, and Wei Zhao for help with predictive technology models.  ... 
doi:10.1109/jproc.2009.2033621 fatcat:ehsup4tsbfa67ccdre7wvt26yq

Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing

Vincent Camusy, Linyan Meiy, Christian Enz, Marian Verhelst
2019 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Circuits are analyzed for each precision as well as jointly in practical use cases, highlighting the impact of architectures and scalability in terms of energy, throughput, area and bandwidth, aiming to  ...  To this end, various precision-scalable MAC architectures optimized for neural networks have recently been proposed.  ...  Serial designs are the only type requiring less area than the conventional multiplier, allowing area savings up to 40% on the MAC circuit for area-constrained systems.  ... 
doi:10.1109/jetcas.2019.2950386 fatcat:37cujuomkzbcvcurpx7oy6xcwu

Energy Efficient Multi-Core Processing

Charles Leech, Tom J. Kazmierski
2014 Electronics  
minimal architectural synthesis technique to achieve greater energy and area efficiency whilst maintaining performance.  ...  This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time  ...  ACKNOWLEDGMENT This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), UK under grant number EP/K034448/1 " PRiME: Power-efficient, Reliable, Many-core Embedded systems  ... 
doi:10.7251/els1418003l fatcat:ehztmbwggvayddswnnp6qxg2ra

Channel Coding for Tbit/s Communications: An Implementation Centric View

Norbert Wehn
2019 Zenodo  
Turbo codes, Low Density Parity Check (LDPC) codes and Polar codes and present decoder architectures for all three code classes that are designed for highest throughput.  ...  transceivers, which have tightly constrained power and energy budgets.  ...  ACKNOWLEDGEMENT We gratefully acknowledge financial support by the EU (project-ID: 760150-EPIC) and the DFG (project-ID: 2442/8-1).  ... 
doi:10.5281/zenodo.3477836 fatcat:d6p6gn66ljej5jyl35tb6mmz4i

An Overview of Sustainable Green 5G Networks [article]

Qingqing Wu, Geoffrey Ye Li, Wen Chen, Derrick Wing Kwan Ng, and Robert Schober
2016 arXiv   pre-print
To enable sustainable 5G networks, new technologies have been proposed to improve the system energy efficiency and alternative energy sources are introduced to reduce our dependence on traditional fossil  ...  In this article, we provide an overview of the latest research on both green 5G techniques and energy harvesting for communication.  ...  This motivates the configuration of low resolution ADCs in practical systems, especially for battery-constrained handheld devices.  ... 
arXiv:1609.09773v2 fatcat:hb3c5i3p4jfcpmgneqpntxwik4

Topologically homogeneous power-performance heterogeneous multicore systems

K Chakraborty, S Roy
2011 2011 Design, Automation & Test in Europe  
Dynamic Voltage and Frequency Scaling (DVFS), a widely adopted technique to ensure safe thermal characteristics while delivering superior energy efficiency, is rapidly becoming inefficient with technology  ...  We use a combination of standard cell library based CAD flow and full system architectural simulation to demonstrate 11-22% improvement in energy efficiency using our design paradigm.  ...  for the nominal frequency, and tend to be power hungry; and (b) forthcoming technology generations are restricting the supply voltage 978-3-9810801-7-9/DATE11/ c 2011 EDAA scaling margins [2] , [12]  ... 
doi:10.1109/date.2011.5763030 dblp:conf/date/ChakrabortyR11 fatcat:sberfoybozcsvbjviuftb5pnpq

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David Blaauw, Dennis Sylvester
2014 IEEE Journal of Solid-State Circuits  
Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed.  ...  A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput  ...  We then apply architectural and circuit techniques including a robust low-power FIFO for subthreshold operation, further reducing power consumption.  ... 
doi:10.1109/jssc.2014.2309692 fatcat:5wambheozngavc3ej2cjduzbrq

Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics

Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram (+2 others)
2008 2008 16th IEEE Symposium on High Performance Interconnects  
Simulation and experimental results reveal an order of magnitude better energy-efficiency than electrical links in the same technology generation.  ...  For a power-constrained system with 256 cores connected to 16 DRAM modules using an opto-electrical crossbar, aggregate network throughput can be improved by ≈8-10× compared to an optimized purely electrical  ...  Acknowledgments The authors acknowledge chip fabrication support from Texas Instruments and partial funding from DARPA MTO/UNIC award W911NF-06-1-0449.  ... 
doi:10.1109/hoti.2008.11 dblp:conf/hoti/BattenJOKMHPLSHKRSA08 fatcat:kxcfc4uwpfexlcveyyw3q24sde
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