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Architectural and physical design challenges for one-million gate FPGAs and beyond

Jonathan Rose, Dwight Hill
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that.  ...  In this paper we describe several challenges that will need to be solved for these large-scale FPGAs to realize their full potential. 1.  ...  The other extreme is to have no buffers at any programmable Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond Jonathan Rose + and Dwight Hill * Department of Electrical  ... 
doi:10.1145/258305.258324 dblp:conf/fpga/RoseH97 fatcat:middzs76z5bfvn36itskd3ct3u

Physical design for FPGAs

Rajeev Jayaraman
2001 Proceedings of the 2001 international symposium on Physical design - ISPD '01  
Apart from allowing FPGA users to implement their designs on FPGAs, FPGA physical design is also used extensively in developing and evaluating new FPGA architectures.  ...  In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements and challenges.  ...  For example, in the same time it took to completely place and route the largest FPGA device of 25000 gates five years ago, it is now not only possible but expected that a multi-million gate design be placed  ... 
doi:10.1145/369691.369776 dblp:conf/ispd/Jayaraman01 fatcat:jp4epw2dcjgpbfwov76xirbmra

Guest Editors' Introduction: Advances in Configurable Computing

P. Lysaght, P.A. Subrahmanyam
2005 IEEE Design & Test of Computers  
These include the authors who submitted articles, the reviewers, the editor in chief, and the editorial and production staff at the IEEE Computer Society.  ...  Today, FPGAs are large and fast enough for use in multimillion-gate designs running at hundreds of megahertz.  ...  The cost per FPGA gate has, as expected, continuously eroded over time. Meanwhile, the total design cost, including nonrecurring engineering charges and design tool costs, has escalated for ASICs.  ... 
doi:10.1109/mdt.2005.36 fatcat:tormrzxfcrfvpnl6ujpeueug64

Special Issue on Reconfigurable Systems: Foundations [Guest editors' introduction]

James Lyke, Christos G. Christodoulou, Alonzo Vera, Art H. Edwards
2015 Proceedings of the IEEE  
In the next paper of this issue, ''High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond,'' Wirthlin highlights some of the challenges in creating reliable reconfigurable systems.  ...  Vera has focussed on embedded system design for aerospace applications, dynamic partial reconfiguration applications using FPGAs, radiation effects mitigation techniques for FPGA-based systems and custom  ... 
doi:10.1109/jproc.2015.2399071 fatcat:ohcaq42svjcztl6q2wwbrfs2wu

Don't forget memories

David Sheldon, Frank Vahid
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
The study involves converting a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs.  ...  Through this and other case studies, design patterns may emerge that aid designers in redesigning ASIC circuits for FPGAs as well as in building new highperformance and efficient circuits for FPGAs.  ...  However, designing circuit architectures for FPGAs involves some important differences from ASICs.  ... 
doi:10.1145/1450135.1450171 dblp:conf/codes/SheldonV08 fatcat:velezxserjapbayfbpiiqxi43q

Multi-million gate FPGA physical design challenges

Maogang Wang, A. Ranjan, S. Raje
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Hierarchical approaches to divide and conquer the design, early estimation tools for design exploration, and physical optimizations are some of the key methodologies that have to be introduced in the FPGA  ...  This paper will investigate the loss/benefit in quality of results due to hierarchical approaches and compare and contrast some of the design automation problem formulations and solutions needed for FPGAs  ...  For a multi-million gate design, the placement tools have around 10 hierarchical levels if the quadrisection method is used.  ... 
doi:10.1109/iccad.2003.159780 fatcat:h66lt6ffijhoneb5xx4q6e7hri

The density advantage of configurable computing

A. DeHon
2000 Computer  
A large and growing community of researchers has successfully used fieldprogrammable gate arrays (FPGAs) to accelerate computing applications.  ...  If we can exploit this advantage across applications, configurable architectures can become an important part of general-purpose computer design.  ...  His research interests include all aspects of physical implementations of computations from substrates up through architectures and mapping, including system abstraction and design.  ... 
doi:10.1109/2.839320 fatcat:m5no7juvrzdb7opzeay32exhlu

Design and Implementation of control Unit-ALU of 32 Bit Asynchronous Microprocessor based on FPGA

Archana Rani, Naresh Grover
2018 International Journal of Engineering and Manufacturing  
The design of asynchronous processor is used to reduce the various challenges faced in synchronous architectures.  ...  This paper further presents the optimization techniques for reducing area power and delay constraints related to digital circuits using FPGA.  ...  of AND or OR gate arrays for CPLDs.Once the synthesis has been done, our next goal is to take our design to the physical working model.  ... 
doi:10.5815/ijem.2018.03.02 fatcat:ssqbjkc2tvac3dn6nqn6xcab44

Molecular electronics

Michael Butts, Andrée DeHon, Seth Copen Goldstein
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
This tutorial reviews emerging molecular-scale electronics technology for CAD and system designers and highlights where ICCAD research can help support this technology.  ...  New electronics technologies are emerging which may carry us beyond the limits of lithographic processing down to molecularscale feature sizes.  ...  Goldstein is funded by the DARPA Moletronics program under grants ONR N00014-01-0659 and MDA972-01-03-0005. Prof. DeHon is funded by the DARPA Moletronics program under grant ONR N00014-01-0651.  ... 
doi:10.1145/774572.774636 dblp:conf/iccad/ButtsDG02 fatcat:4g3mjkn2bvdmnmz3nb5wrtryp4

Monolithically stackable hybrid FPGA

Dmitri Strukov, Alan Mishchenko
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic architectures.  ...  design rules and similar power density.  ...  (c, d, g) Half adder circuit mapping using NAND/AND gates, and MUX gates with two different style, and (b, e, h) their corresponding physical mapping to CMOL FPGA circuit (with effective one layer connectivity  ... 
doi:10.1109/date.2010.5457117 dblp:conf/date/StrukovM10 fatcat:74d2dcv6ufd45f3plr2c2w5pje

Development of on Board, Highly Flexible, Galileo Signal Generator ASIC

Louis Baguena, Emmanuel Liegeon, Alexandra Bepoix
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
A conclusion will then be drawn on the requirements on technology and tools for space domain. 978-3-9810801-2-4/DATE07 © 2007 EDAA  ...  It will then present the ASIC and the development flow of this project, emphasizing the up to date tools that have been used (architectural synthesis, physical synthesis).  ...  tools: one at the high level design, one at the physical design stage.  ... 
doi:10.1109/date.2007.364673 dblp:conf/date/BaguenaLBDOBH07 fatcat:2aefcfh4qnaitpxqofexf6xhsy

Reconfigurable Asynchronous Logic

Rajit Manohar
2006 IEEE Custom Integrated Circuits Conference 2006  
We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture.  ...  The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.  ...  However, mapping these circuits to a reconfigurable fabric creates challenges beyond those present in conventional clocked circuits.  ... 
doi:10.1109/cicc.2006.320939 dblp:conf/cicc/Manohar06 fatcat:qexbzzoz4rfo5klxmae2xliady

Run-time support for dynamically reconfigurable computing systems

Martyn Edwards, Peter Green
2003 Journal of systems architecture  
This research paper introduces the reconfigurable computing from its hardware and software perspectives being existent and further demanded for future work and emerging research dimensions in this area  ...  The main theme beyond this new technology is to integrate the performance benefits of application specific integrated circuits with the hardware flexibility of programmable processors in a single chip.  ...  million logic gates.  ... 
doi:10.1016/s1383-7621(03)00068-7 fatcat:weqgn7zw6ndcpggtkwcfcgtj44

Towards 100G packet processing: Challenges and technologies

Christian Hermsmeyer, Haoyu Song, Ralph Schlenk, Riccardo Gemelli, Stephan Bunse
2009 Bell Labs technical journal  
The state-of-the-art architectures and algorithms for every aspect of packet processing are described.  ...  The evolution of field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technology was analyzed concerning speed, density, power, and pin interfacing.  ...  Acknowledgements We acknowledge gratefully that part of this work has been supported by the German Ministry for Research and Education (BMBF) under the EUREKA project "100GET-100Gbit/s Carrier-Grade Ethernet  ... 
doi:10.1002/bltj.20373 fatcat:nc5upq6ga5blnmnyuuy4r3hn6y

Logic emulation with virtual wires

J. Babb, R. Tessier, M. Dahl, S.Z. Hanono, D.M. Hoki, A. Agarwal
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45%.  ...  Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires, and pipelining these connections at the maximum clocking frequency of the FPGA.  ...  Since this work, FPGA-based logic emulation systems have been developed for design complexity ranging from several thousand to several million gates.  ... 
doi:10.1109/43.640619 fatcat:xslresgiivbi7pjbujhtecivii
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