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Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor

Jian Wang, Joar Sohl, Dake Liu
2010 2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing  
This paper presents the architectural support in an embedded multiprocessor platform to maximally reduce the parallel processing overhead.  ...  Implementing an algorithm in a parallel platform usually produces control and communication overhead which is not parallelizable.  ...  ACKNOWLEDGEMENTS The authors would like to thank SSF, Swedish Foundation for Strategic Research, for the support of this project.  ... 
doi:10.1109/euc.2010.17 dblp:conf/euc/WangSL10 fatcat:uboiys3jzncufgqeana4pn7lxy

Towards multiprocessor sensor nodes

Utz Roedig, Sarah Rutlidge, James Brown, Andrew Scott
2010 Proceedings of the 6th Workshop on Hot Topics in Embedded Networked Sensors - HotEmNets '10  
This paper presents the results of an early experimental study into the benefits of using a multiprocessor sensor node architecture.  ...  The study shows that the desired hardware configuration flexibility can be achieved with relatively low overheads while supporting established sensor node programming concepts.  ...  Depending on implementation and application, processing overheads for context switching on a single processor system may also be higher than processing overheads for communication in a multiprocessor system  ... 
doi:10.1145/1978642.1978663 dblp:conf/emnets/RoedigRBS10 fatcat:fwejlqxuv5euxf7ke6bunzi5qm

Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  To enable MP-SoC platforms, scalable communicationcentric interconnect fabrics, such as networks-on-chip (NoC), have been recently proposed.  ...  Interconnection The interconnect is the key element of the multiprocessor system, since it provides low latency communication layer, capable of minimizing the overhead due to thread spawning and synchronization  ... 
doi:10.1109/icsamos.2006.300821 dblp:conf/samos/MonchieroPSV06 fatcat:cu6537637na4vgk3bfthdjxuoe

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 Journal of systems architecture  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  To enable MP-SoC platforms, scalable communicationcentric interconnect fabrics, such as networks-on-chip (NoC), have been recently proposed.  ...  Interconnection The interconnect is the key element of the multiprocessor system, since it provides low latency communication layer, capable of minimizing the overhead due to thread spawning and synchronization  ... 
doi:10.1016/j.sysarc.2007.01.008 fatcat:6jjvd42x2vetdmai3ftipxlg5e

The impact of communication locality on large-scale multiprocessor performance

Kirk L. Johnson
1992 SIGARCH Computer Architecture News  
Introduction At the heart of any multiprocessor lies the interconnection network through which processing nodes communicate with one another.  ...  , future large-scale multiprocessors will probably use some type of non-uniform communication latency (NUCL) interconnection network (e.g. meshes, trees).  ...  due to fixed transaction overhead and actual CPU cycles is reduced.  ... 
doi:10.1145/146628.140403 fatcat:4xy5gxdbeffchppmbeywhxkphe

Environment for multiprocessor simulator development

Masaki Wakabayashi, Hideharu Amano
2003 Electronics and communications in Japan. Part 3, Fundamental electronic science  
ISIS, an architecture independent simulation kit for multiprocessors, is developed so as to reduce such designers load.  ...  ISIS users can build simulators for their original target architectures only by connecting "Units" each other. The implementation cost is much reduced with little runtime overhead.  ...  Snoop Interconnection Network Simulator ISIS had been used for the evaluation of interconnection network used in a massively parallel computer JUMP-1 [3] which was developed with cooperation of seven  ... 
doi:10.1002/ecjc.10122 fatcat:pkhr2iaxebcapiecxa6daabs4a

The impact of communication locality on large-scale multiprocessor performance

Kirk L. Johnson
1992 Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92  
Introduction At the heart of any multiprocessor lies the interconnection network through which processing nodes communicate with one another.  ...  , future large-scale multiprocessors will probably use some type of non-uniform communication latency (NUCL) interconnection network (e.g. meshes, trees).  ...  due to fixed transaction overhead and actual CPU cycles is reduced.  ... 
doi:10.1145/139669.140403 dblp:conf/isca/Johnson92 fatcat:az2rz34vwncbzd5ubv7dr5yl34

A New Token-Based Channel Access Protocol for Wavelength Division Multiplexed Multiprocessor Interconnects

Joon-Ho Ha, Timothy Mark Pinkston
2000 Journal of Parallel and Distributed Computing  
This paper presents a token-based channel access protocol for wavelength division multiplexed optically interconnected multiprocessors.  ...  for networks supporting point-to-point communication offered by WDM (e.g., PTP and Hybrid).  ...  There is a number of proposed distributed channel access protocols for use in optical multiprocessor interconnects.  ... 
doi:10.1006/jpdc.1999.1599 fatcat:lofnf7nlmrbtnernbfbf6exsry

Application Specific Customization and Scalability of Soft Multiprocessors

Deepak Unnikrishnan, Jia Zhao, Russell Tessier
2009 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines  
The entire communication is specified at compile time in the static network, while the dynamic network supports run time events.  ...  Point-to-point topologies gain significant cycle speedups due to reduced synchronization overhead from the elimination of network hops.  ... 
doi:10.1109/fccm.2009.41 dblp:conf/fccm/UnnikrishnanZT09 fatcat:7cjy7ltl4rcyzlo7e2p4hdecdq

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
By scaling a problem to a sufficiently large size to reduce the computation to communication ratio, overhead can be reduced to increase processing rates.  ...  The interconnect network must be generation scalable over at least a decade to support binary compatibility of apps among generations!  ...  Another requirement for evolvability is that the network must be improved to have reduced overhead and latency in proportion to the processor speedup.  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

Workload adaptive shared memory multicore processors with reconfigurable interconnects

Shoaib Akram, Rakesh Kumar, Deming Chen
2009 2009 IEEE 7th Symposium on Application Specific Processors  
Interconnection networks for multicore processors are designed in a generic way to serve a diversity of workloads.  ...  Reconfigurable logic is inserted between clusters to support either isolation or different policies for communication among clusters.  ...  Lu Wan of the ECE department of University of Illinois-Urbana Champaign for helpful discussions.  ... 
doi:10.1109/sasp.2009.5226329 dblp:conf/sasp/AkramKC09 fatcat:hdtw4eotx5fuzjaho2k75vjkoe

Modeling and Simulative Performance Analysis of SMP and Clustered Computer Architectures

Mark W. Burns, Alan D. George, Brad A. Wallace
2000 Simulation (San Diego, Calif.)  
, and network transactions is used to quantify the communication overhead of each system.  ...  Because the performance of a parallel algorithm on a specific architecture is dependent upon its communication-to-computation ratio, an analysis of communication latencies for bus transactions, cache coherence  ...  For simulation of distributed systems, an accurate interconnection network model is a necessity because of the overhead associated with interprocessor (or intercluster) communication.  ... 
doi:10.1177/003754970007400203 fatcat:t3aac62snrchdb4yojb5fnuvja

Design, Synthesis, and Test of Networks on Chips

P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli
2005 IEEE Design & Test of Computers  
Regular network architectures are well suited for the realization of multiprocessor communication schemes.  ...  Kumar proposed a mesh-based interconnect architecture called Cliché (Figure 1a ). 5 Grecu et al. 6 describe an interconnect architecture based on the butterfly fat-tree (BFT) topology for a networked  ... 
doi:10.1109/mdt.2005.108 fatcat:ftg32fzp2jelppgskbqb34ehiy

Page 879 of IEEE Transactions on Computers Vol. 52, Issue 7 [page]

2003 IEEE Transactions on Computers  
“Effects of Communication Latency, Overhead, Proc. 24th Int'l Symp Cc ymip vol R.P and Bandwidth in a Cluster Architecture,’ Computer Architecture, pp. 85-97, June 1997 M. Michael at al.  ...  Tang, “A Novel Reduce Cache Invalidation Overheads in 19th IEEE Int'l Performance, Computing, and Comm. Conf Feb. 2000 Multicast Scheme to DSM Systems,” Prox pp 597 603  ... 

Dynamic Scheduling Algorithm for Variants of Hypercube Interconnection Networks

Zaki Ahmad Khan, Jamshed Siddiqui, Mahfooz Alam
2017 Indian Journal of Science and Technology  
Method/Statistical Analysis: The dynamic task scheduling algorithm has been proposed for scheduling the load on numerous cube based multiprocessor interconnection networks.  ...  Especially the efficiency of the proposed algorithm is examined in terms of performance parameters for instance Load Imbalance Factor's as well as Execution Time for cube based multiprocessor networks;  ...  With in this paper top three cubes based multiprocessor interconnection networks are thought meant for simulation.  ... 
doi:10.17485/ijst/2017/v10i25/105344 fatcat:fykvwbailffnrd3ypebovj3a5q
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