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Architectural support for parallel reductions in scalable shared-memory multiprocessors

M.J. Garzaran, M. Prvulovic, Ye Zhang, A. Jula, Hao Yu, L. Rauchwerger, J. Torrellas
Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques  
In this paper, we present new architectural support that significantly speeds-up parallel reduction and makes it scalable in shared-memory multiprocessors.  ...  Unfortunately, conventional reduction parallelization algorithms are not scalable.  ...  Acknowledgments This work was supported in part by the National Science Foundation under grants CCR-9734471, ACI-9872126, EIA-9975018, CCR-9970488, EIA-0081307, and EIA-0072102; CI-CYT of Spain under grant  ... 
doi:10.1109/pact.2001.953304 dblp:conf/IEEEpact/GarzaranPZTJYR01 fatcat:5hubuykugjdmzdmpzpxsmytzye

Trends in shared memory multiprocessing

P. Stenstrom, E. Hagersten, D.J. Lilja, M. Martonosi, M. Venugopal
1997 Computer  
The second step is to begin filling gaps in programming models and architectures for shared memory multiprocessing.  ...  P rogress in shared memory multiprocessing research has led to its industrial recognition as a key technology for application domains such as decision support systems and multimedia processing.  ...  Acknowledgments We thank Yale Patt, who initiated the set of task forces that allowed us to develop our thoughts in a creative environment in Hawaii.  ... 
doi:10.1109/2.642814 fatcat:mhsgglxwfvdrtc4c4ap6eshxxa

A comprehensive bibliography of distributed shared memory

M. Rasit Eskicioglu
1996 ACM SIGOPS Operating Systems Review  
Shared memory is an attractive programming model for designing parallel and distributed applications.  ...  DSM has been implemented both in software (e.g., to provide the shared memory programming model on networks of workstations) and in hardware (e.g., using cache consistency protocols to support shared memory  ...  T-Zero: Hardware Support for Distributed Shared Memory on a Cluster of Workstations. In Proc. of the Fifth Workshop on Scalable Shared Memory Multiprocessors, June 1995.  ... 
doi:10.1145/218646.218651 fatcat:ildcgoxumvheharepblsrqm5ui

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
KEY WORDS: Scalable multiprocessors and multicomputers; massive parallelism; distributed or shared virtual memory; high performance computers; computer architecture.  ...  The parameters that determine these structures and their utility include: whether hardware (a multiprocessor) or software (a multicomputer) is used to maintain a distributed, or shared virtual memory (  ...  Two, massively parallel computer structures have been introduced in a race to provide a "peak" teraflop of computing power (Bell")) by 1995: the scalable, shared memory multiprocessor (smP) and the scalable  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

Toward Large-Scale Shared Memory Multiprocessing [chapter]

John K. Bennett, John B. Carter, Willy Zwaenepoel
1992 Scalable Shared Memory Multiprocessors  
multiprocessor with extensive hardware support for scalability.  ...  Munin allows parallel programs written for shared memory multiprocessors to be executed e ciently on distributed memory multiprocessors.  ...  ACKNOWLEDGEMENTS Other members of the Computer Systems Laboratory have participated in the development o f m a n y of the ideas that we h a ve presented.  ... 
doi:10.1007/978-1-4615-3604-8_15 fatcat:k7qiuyjnbzc5bkx4eenkrzmvxq

OpenMP: an industry standard API for shared-memory programming

L. Dagum, R. Menon
1998 IEEE Computational Science & Engineering  
A class of multiprocessor architectures is now emerging that offers scalable hardware support for cache coher-46  ...  This article compares OpenMP to existing parallel-programming models. pplication developers have long recognized that scalable hardware and software are necessary for parallel scalability in application  ...  These are generally called scalable shaved memory ~ultip~ocessov architectures.'  ... 
doi:10.1109/99.660313 fatcat:hxvskz2vmvbwheklyzc2wn4xci

Author index

2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
hardware FPGA SAR Processor with Optimal Window Memory Layout An effi cient SIMD architecture with parallel memory for 2D cosine transforms of video coding A Triplet Based Computer Architecture Supporting  ...  Parallel Object Computing ISA Support for Fingerprinting and Erasure Codes Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors Reconfi gurable Motion Estimation Architecture  ... 
doi:10.1109/asap.2007.4459300 fatcat:lbxlom2lkrf2jf3q5c56uwiuea

Page 631 of IEEE Transactions on Computers Vol. 52, Issue 5 [page]

2003 IEEE Transactions on Computers  
details of a Switch MSHR (SMSHR) architecture and an SMSHR+cache architecture to reduce the remote memory access time in CC-NUMA multiprocessors.  ...  Snir, “The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer,” JEEE Trans.  ... 

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 Journal of systems architecture  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1016/j.sysarc.2007.01.008 fatcat:6jjvd42x2vetdmai3ftipxlg5e

Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1109/icsamos.2006.300821 dblp:conf/samos/MonchieroPSV06 fatcat:cu6537637na4vgk3bfthdjxuoe

A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors [chapter]

Alberto Ros, Manuel E. Acacio, José M. García
2005 Lecture Notes in Computer Science  
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to the indirection introduced  ...  Results demonstrate that the lightweight directory architecture achieves better performance than a non-scalable full-map directory, with a very significant reduction on directory memory overhead.  ...  Acknowledgments This work has been supported by the Spanish Ministry of Ciencia y Tecnología and the European Union (Feder Funds) under grant TIC2003-08154-C06-03.  ... 
doi:10.1007/11549468_65 fatcat:t67l6qxu4zealpmrie7lxrapfm

Cache-coherent distributed shared memory: perspectives on its development and future challenges

J. Hennessy, M. Heinrich, A. Gupta
1999 Proceedings of the IEEE  
Distributed shared memory is an architectural approach that allows multiprocessors to support a single shared address space that is implemented with physically distributed memories.  ...  Hardware-supported distributed shared memory is becoming the dominant approach for building multiprocessors with moderate to large numbers of processors.  ...  Bus-based, shared-memory multiprocessors remain the dominant multiprocessor architecture for small processor counts.  ... 
doi:10.1109/5.747863 fatcat:koqfmkqdibaylcxfiheb33bwly

Design of a scalable multiprocessor architecture and its simulation

Der-Lin Pean, Chao-Chin Wu, Huey-Ting Chua, Cheng Chen
2001 Journal of Systems and Software  
Several new issues in our architecture, including scalable cache coherence protocols, relaxed memory consistency models, memory optimization techniques and several types of processors are considered.  ...  A scalable cluster-based multiprocessor architecture and its simulation environment called SEECMA are proposed.  ...  Acknowledgements This research was supported by the National Science Council of the Republic of China under contract number NSC 87-2213-E009-049.  ... 
doi:10.1016/s0164-1212(01)00034-6 fatcat:ix6rj2i3grfbfgk3ha23bd4udq

Extending OpenMP for heterogeneous chip multiprocessors

F. Liu, V. Chaudhary
2003 2003 International Conference on Parallel Processing, 2003. Proceedings.  
In this paper, we propose that high-level abstraction of parallel programming like OpenMP is suitable for chip multiprocessors.  ...  Several optimization techniques are proposed to utilize advanced architecture features of our target SOC, the Software Scalable System on Chip (3SoC).  ...  Singh for his contribution of the Double Buffering concept.  ... 
doi:10.1109/icpp.2003.1240577 dblp:conf/icpp/LiuC03 fatcat:qg25r3k6unazviftohe6z7pvoa

Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation [article]

Kevin Andryc, Tedy Thomas, Russell Tessier
2016 arXiv   pre-print
The overlay architecture is optimized for FPGA implementation to support efficient use of embedded block memories and DSP blocks.  ...  Issues related to scaling the overlay architecture to multiple GPGPU multiprocessors are considered along with application-class architectural optimizations.  ...  These architectures typically support a customizable number of operations performed in parallel, an optimized memory interface, and a compiler.  ... 
arXiv:1606.06454v1 fatcat:ckqxsfqfj5gl7bresimoycrvke
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