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Instruction Set Extensions for Fast Arithmetic in Finite Fields GF(p) and GF(2 m )
[chapter]
2004
Lecture Notes in Computer Science
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The custom instructions can be easily integrated into a standard RISC architecture like MIPS32 and require only little extra hardware. ...
In this paper we introduce a set of five custom instructions to accelerate arithmetic operations in finite fields GF(p) and GF(2 m ). ...
The first author was supported by the Austrian Science Fund (FWF) under grant number P16952-N04 ("Instruction Set Extensions for Public-Key Cryptography"). ...
doi:10.1007/978-3-540-28632-5_10
fatcat:sbaonlajqzdarn6alni4t3uz4m
Elliptic Curve Cryptography on Smart Cards without Coprocessors
[chapter]
2000
Smart Card Research and Advanced Applications
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We focus in this paper on the Intel 8051 family of microcontrollers popular in smart cards and other cost-sensitive devices. ...
The implementation is based on the use of the finite field GF ((2 8 − 17) 17 ) which is particularly suited for low end 8-bit processors. ...
ACKNOWLEDGEMENTS The authors would like to thank Jorge Guajardo and Pedro Soria-Rodriguez for their contribution of the even composite field multiplication implementation. ...
doi:10.1007/978-0-387-35528-3_5
fatcat:epuxwk5jkvfoffko3hdcfdk56q
High-speed implementation of an ECC-based wireless authentication protocol on an ARM microprocessor
2001
IEE Proceedings - Communications
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With these timings, the execution of the ECC-based wireless authentication protocol takes around 140ms on the ARM7TDMI processor, which is a widely used, low-power core processor for wireless applications ...
A practical software library has been produced which supports variable length implementation of the elliptic curve digital signature algorithm (ECDSA). ...
It supports long key lengths providing security for highvalue or very long-term applications. ...
doi:10.1049/ip-com:20010511
fatcat:4vplnqaynnfoxk57lxwfnezjei
A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography
2008
2008 International Conference on Electronic Design
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This work presents the implementation of a tightlycoupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. ...
The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. ...
Previous work reported in [8] [9] focused on the ARMv4 architecture and proposed architectural enhancements to support long integer modular arithmetic. ...
doi:10.1109/iced.2008.4786692
fatcat:g4parykmfzg3dcrbvod4x34djq
A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography
2009
International Journal of Information and Communication Technology
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This work presents the implementation of a tightlycoupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. ...
The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. ...
Previous work reported in [8] [9] focused on the ARMv4 architecture and proposed architectural enhancements to support long integer modular arithmetic. ...
doi:10.1504/ijict.2009.026430
fatcat:carwkghctvcffj34gh5a3wkzvy
ISA Extensions for Finite Field Arithmetic
2020
Transactions on Cryptographic Hardware and Embedded Systems
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We present and evaluate a custom extension to the RISC-V instruction set for finite field arithmetic. ...
To that end, we also present an optimized software implementation for the standard RISC-V instruction set for the polynomial arithmetic underlying those schemes, which serves as basis for comparison. ...
The work of EA was partially supported by the German Federal Ministry of Education and Research and the Hessen State Ministry for Higher Education, Research and the Arts within their joint support of the ...
doi:10.13154/tches.v2020.i3.219-242
dblp:journals/tches/AlkimELNP20
fatcat:phf55xxoqvefpf4osl6os5k2xu
ISA Extensions for Finite Field Arithmetic - Accelerating Kyber and NewHope on RISC-V
[article]
2020
IACR Cryptology ePrint Archive
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We present and evaluate a custom extension to the RISC-V instruction set for finite field arithmetic. ...
To that end, we also present an optimized software implementation for the standard RISC-V instruction set for the polynomial arithmetic underlying those schemes, which serves as basis for comparison. ...
Other software-based works on constrained devices in the area of lattice-based schemes are an implementation of NTRU [BSJ15] on a smart card microprocessor, of BLISS on ARM Cortex-M4F microcontroller ...
dblp:journals/iacr/AlkimELNP20
fatcat:gtbo4aq2brfhfmr2syg3vaahji
FPGA Implementation of RISC-based Memory-centric Processor Architecture
2019
International Journal of Advanced Computer Science and Applications
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In order to alleviate the processor-memory bottleneck, in this paper we are proposing a RISC-based memory-centric processor architecture that provides a stronger merge between the processor and the memory ...
Indeed, we are developing a RISC-based processor that integrates the memory into the same chip die, and thus provides direct access to the on-chip memory, without the use of general-purpose registers ( ...
DESIGN OF RISC-BASED MEMORY-CENTRIC PROCESSOR ARCHITECTURE As a referencing point for designing the proposed RISCbased memory-centric processor, we make use of a RISC architecture implementation (MIPS) ...
doi:10.14569/ijacsa.2019.0100902
fatcat:gcz54vcfxvaezdw7lodxzuw7ea
Future wireless convergence platforms
2005
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05
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From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. ...
The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis. ...
This creates a challenge for high-level language implementations that specify integer modulo arithmetic. Therefore, most DSPs have been programmed using assembly language. ...
doi:10.1145/1084834.1084841
dblp:conf/codes/GlossnerMINJSSRSV05
fatcat:6gigbaib6zgqtht3356k4mhqfu
Efficient Implementation of Elliptic Curve Cryptosystems on the TI MSP430x33x Family of Microcontrollers
[chapter]
2001
Lecture Notes in Computer Science
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We used a Generalized-Mersenne prime to implement the arithmetic in the underlying field. ...
We modified the EC point addition and doubling formulae to reduce the number of intermediate variables while at the same time allowing for flexibility. ...
Reference [34] focuses on the implementation of ECC on the 8051 family of microcontrollers, popular in smart cards. ...
doi:10.1007/3-540-44586-2_27
fatcat:eywmsyw2brh65mejsnxhq22osu
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
[chapter]
2006
Lecture Notes in Computer Science
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8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. ...
In this paper we present a minimalist hardware accelerator for enabling elliptic curve cryptography (ECC) on an 8051 microcontroller. ...
The research described in this paper was supported by the Austrian Science Fund under grant P16952-NO4 "Instruction Set Extensions for Public-Key Cryptography" and in part by the European Commission through ...
doi:10.1007/11894063_34
fatcat:2ue2f5jtkrd37jlyjmtg3j4h5u
Hardware Acceleration of the Tate Pairing in Characteristic Three
[chapter]
2005
Lecture Notes in Computer Science
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As a result we reason that even on constrained devices one can usefully evaluate the pairing, a fact that gives credence to the idea that identity based cryptography is an ideal partner for identity aware ...
In this paper we prototype and evaluate polynomial and normal basis field arithmetic on an FPGA device and use it to construct a hardware accelerator for pairings over fields of characteristic three. ...
Acknowledgements The authors would like to thank Rob Granger, Johann Großschädl, Elisabeth Oswald, Nigel Smart, Martijn Stam and Fré Vercauteren for invaluable help and support throughout the course of ...
doi:10.1007/11545262_29
fatcat:prtjbvglarh4nan47fpmi6x3d4
Low-Weight Primes for Lightweight Elliptic Curve Cryptography on 8-bit AVR Processors
[chapter]
2014
Lecture Notes in Computer Science
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Small 8-bit RISC processors and micro-controllers based on the AVR instruction set architecture are widely used in the embedded domain with applications ranging from smartcards over control systems to ...
The former uses a GLV curve and executes in 4.19 M cycles (over a 160-bit OPF), while the latter is based on a Montgomery curve and has an execution time of approximately 5.93 M cycles. ...
of smart cards, wireless sensor nodes, and similar kinds of embedded devices. ...
doi:10.1007/978-3-319-12087-4_14
fatcat:6rd3vap2xbfjda5q46vfgmswie
The Sandbridge SB3011 Platform
2007
EURASIP Journal on Embedded Systems
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We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. ...
Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. ...
This creates a challenge for high-level language implementations that specify integer modulo arithmetic. Therefore, most DSPs have been programmed using assembly language. ...
doi:10.1186/1687-3963-2007-056467
fatcat:uuo67bgefzetpdlm6246mkjdja
The Sandbridge SB3011 Platform
2007
EURASIP Journal on Embedded Systems
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We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. ...
Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. ...
This creates a challenge for high-level language implementations that specify integer modulo arithmetic. Therefore, most DSPs have been programmed using assembly language. ...
doi:10.1155/2007/56467
fatcat:gicryhrnojgjngvd35vfkmhrhe
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