Filters








2,103 Hits in 6.9 sec

Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results

D.I. August, D.A. Connors, J.C. Gyllenhaal, W.-M.W. Hwu
Proceedings Third International Symposium on High-Performance Computer Architecture  
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication.  ...  In compiler-synthesized dynamic branch prediction, the compiler generates code sequences that, when executed, digest relevant state information and execution statistics into a condition bit, or predicate  ...  Acknowledgments The authors would like to thank all the members of the IMPACT compiler team for their support.  ... 
doi:10.1109/hpca.1997.569617 dblp:conf/hpca/AugustCGH97 fatcat:x5xfvu4lfjbcpoferykymojgba

Strategy for an Autonomous Behavior that Guarantees a Qualitative Fine Adjustment at the Target Pose of a Collaborating Mobile Robot

Kai Waelti
2021 Zenodo  
As a basis for this strategy, an extensible software architecture for socially acceptable navigation of mobile robots is designed and implemented using ROS components.  ...  in dynamic environments over time.  ...  At the same time, this design strategy considers how to synthesize the sub-problems for solving the original problem.  ... 
doi:10.5281/zenodo.4742013 fatcat:637baqamlffkfda5cvvxzegyuy

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

Nathan Clark, Jason Blome, Michael Chu, Scott Mahlke, Stuart Biles, Krisztian Flautner
2005 SIGARCH Computer Architecture News  
A simple microarchitectural interface is provided to support a plug-and-play model for integrating a wide range of accelerators into a pre-designed and verified processor core.  ...  The compiler is responsible for identifying profitable subgraphs, while the hardware handles discovery, mapping, and execution of compatible subgraphs.  ...  This research was supported in part by ARM Limited, the National Science Foundation grants CCR-0325898 and CCF-0347411, and equipment donated by Hewlett-Packard and Intel Corporation.  ... 
doi:10.1145/1080695.1069993 fatcat:2mqcqdq7fnh3hmuoskk6czjqpy

Metabolic Control Analysis: A Tool for Designing Strategies to Manipulate Metabolic Pathways

Rafael Moreno-Sánchez, Emma Saavedra, Sara Rodríguez-Enríquez, Viridiana Olín-Sandoval
2008 Journal of Biomedicine and Biotechnology  
The different MCA experimental approaches developed for the determination of the flux-control distribution in several pathways are described.  ...  Moreover, MCA helps to understand (i) the underlying mechanisms by which a given enzyme exerts high or low control and (ii) why the control of the pathway is shared by several pathway enzymes and transporters  ...  of the metabolic pathway architecture: due to cell economy and for reaching the highest efficiency, pathway control must reside in the enzymes localized at the beginning of a pathway or after a branch  ... 
doi:10.1155/2008/597913 pmid:18629230 pmcid:PMC2447884 fatcat:voggncbmv5amvap54uymxbvovm

The Mips R10000 superscalar microprocessor

K.C. Yeager
1996 IEEE Micro  
optimization is less effective for the scalar values of many integer applications, because the compiler has difficulty predicting which instructions will generate cache misses The RlOOOO design includes  ...  time-critical control logic in full custom design, making wide use of dynamic and latch-based logic We synthesized the less critical circuits using static register-based logic 28 IEEEMicro  ...  Our renaming strategy, however, dynamically maps the logical-register numbers into physical-register numbers. The processor writes each new result into a new physical register.  ... 
doi:10.1109/40.491460 fatcat:6jupjmwx7bartilm7rrji2jbeu

Automated Vertical Migration to Dynamic Microcode: An Overview and Example

R.I. Winner, E.M. Carter
1986 IEEE Software  
be run on machines and (2) optimize performance for the most likely applications-resulting in architectures tuned for a specific problem class.  ...  Primitives (abstract type-oriented migration) and will discuss and relate a supporting an abstract data type (a queue data structure, for examgeneral dynamic microprogramming management scheme to the ple  ...  Taken to its logical conclusion, one could synthesize an optimum microimage set for Best-possible and best-available selection strategies. We have a known system workload (perhaps a singleton).  ... 
doi:10.1109/ms.1986.233748 fatcat:jwa7n4xmsnej7p5lwvi3hhzf2q

Building timing predictable embedded systems

Philip Axer, Christine Rochange, Maurice Sebastian, Reinhard Von Hanxleden, Reinhard Wilhelm, Wang Yi, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson (+2 others)
2014 ACM Transactions on Embedded Computing Systems  
We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design.  ...  We present techniques for achieving timing predictability on multicores.  ...  Dynamic branch prediction, cache-like structures, and branch history tables increase history dependence even more. All these features influence execution time.  ... 
doi:10.1145/2560033 fatcat:vyvehgnkxfdmnbs2wcwada3sxi

Software speculative multithreading for Java

Christopher J. F. Pickett
2007 Companion to the 22nd ACM SIGPLAN conference on Object oriented programming systems and applications companion - OOPSLA '07  
Results for SPEC CPU2000 were similarly pessimistic [40] . Our initial work on a completely automatic software solution for Java also indicated extremely high overheads [63, 64] .  ...  A large number of novel SpMT hardware architectures and compilers that target them have been evaluated [38] .  ...  Our initial profiling results indicate three main areas for optimization [63] . First, return value prediction accounts for as much as 20% of thread overhead.  ... 
doi:10.1145/1297846.1297950 dblp:conf/oopsla/Pickett07 fatcat:6zydjc6hwbflvfstmm574e2nam

Optimal Water Quality Management Strategies for Urban Watersheds Using Macrolevel Simulation and Optimization Models

Mohammad Tufail, Lindell Ormsbee
2009 Journal of water resources planning and management  
The resulting optimal management model obtained by linking macro-level simulation models with efficient optimization models is capable of identifying optimal management strategies for an urban watershed  ...  Finally, the optimal management model is applied to a real world urban watershed to evaluate management strategies for water quality management leading to the selection of near-optimal strategies.  ...  These readings are taken every 15 minutes and can be compiled into hourly and daily data for a study period.  ... 
doi:10.1061/(asce)0733-9496(2009)135:4(276) fatcat:sgkpxaqekbcftiheh4zsfjtjce

Model-Driven Engineering of Self-Adaptive Software with EUREMA

Thomas Vogel, Holger Giese
2014 ACM Transactions on Autonomous and Adaptive Systems  
Thus, EUREMA supports development by making feedback loops explicit at a higher level of abstraction and it enables solutions where multiple feedback loops interact or operate on top of each other and  ...  Megamodels are kept alive at runtime and by interpreting them, they are directly executed to run feedback loops. Additionally, they can be dynamically adjusted to adapt feedback loops.  ...  The language for expressing conditions to exclusively branch the control flow in FLDs is defined by a grammar, implemented with the Java Compiler Compiler (JavaCC), and embedded in EUREMA.  ... 
doi:10.1145/2555612 fatcat:xy4ztgzrgvd73c2bentys3ai3u

Compilers and Computer Architecture

W.A. Wulf
1981 Computer  
The interactions between the design of a computer's instruction set and the design of compilers that generate code for that computer have serious implications for overall computational cost and efficiency  ...  In turn, finding these algorithms has led us to critically examine many architectures and the problems they pose.  ...  His research interests span the fields traditionally called "programming systems" and "computler architecture."  ... 
doi:10.1109/c-m.1981.220527 fatcat:fs7ulnnfoje2xl77erlnwfcdwm

Software Architecture Knowledge Management

Hans van Vliet
2008 Australian Software Engineering Conference : Proceedings  
• Provide a body of knowledge of software architectural knowledge by describing relevant and useful results from software architecture research and practice.  ...  and evaluating better architectures for their mission-and business-critical systems.  ...  Acknowledgements We are most thankful to the many authors we invited to contribute a chapter within the scope and contents prescribed by us.  ... 
doi:10.1109/aswec.2008.4483186 fatcat:xwdaitrejvb2fkyx3ymeg6tq6i

Area and Power Modeling for Networks-on-Chip with Layout Awareness

Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini
2007 VLSI design (Print)  
In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization  ...  The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility.  ...  Third, we synthesize several configurations (training set) of the target switch architecture in a 0.13 µm technology library with Design Compiler [24] , and measure the corresponding area and power consumption  ... 
doi:10.1155/2007/50285 fatcat:iynxzgm44jcahkfmyqpahfww3y

STEP

Rhodes Brown, Karel Driesen, David Eng, Laurie Hendren, John Jorgensen, Clark Verbrugge, Qin Wang
2002 Proceedings of the 2002 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering - PASTE '02  
The system consists of a trace data definition language along with a compiler for the language and an encoding architecture that implements a number of common trace compaction techniques.  ...  Initial results indicate that compressed Step encodings are often substantially more compact than similarly compressed naïve formats. i ii Constructing Step and this thesis was a personal struggle for  ...  More recently, hardware developers have also used tracing in the development of branch prediction architectures [EPCP98, FFW98, Wu02].  ... 
doi:10.1145/586094.586103 dblp:conf/paste/BrownDEHJVW02 fatcat:m25fiqkmvjckvpxr3gbnfghb64

Explainable AI in Internet of Control System Distributed at Edge-Cloud Architecture

Mehdi Roopaei, Hunter Durian, Joey Godiska
2021 International Journal of Engineering and Advanced Technology  
The IoCS attempts to unleash AI services using resources at the edge near the autonomous agents and make intelligent edge for dynamic, adaptive, and optimized AI control.  ...  In complicated dynamic and unstructured environments such as autonomous vehicles, control systems must be able to deal with more and more complex state situations.  ...  Firstly, initial plans must be synthesized for achieving the goal at hand. These plans can be re-synthesized or re-planned if there is any sort of failure in achieving the goal.  ... 
doi:10.35940/ijeat.c2246.0210321 fatcat:yft4airnknefjoayljdf2rl3va
« Previous Showing results 1 — 15 out of 2,103 results