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TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC

W. Klingauf, H. Gadke, R. Guinzel
2006 Proceedings of the Design Automation & Test in Europe Conference  
Configurability: Each TLM channel of the high-level system model should be represented by a virtual communication channel in the implementation model. Virtual 3-9810801-0-6/DATE06  ...  Flexibility: The hardware part of the architecture should be highly flexible and scalable, enabling each processor core to be connected to an arbitrary number of on-chip communication networks.  ...  Moreover, the HAL should be highly portable in terms of supported target architectures and operating systems.  ... 
doi:10.1109/date.2006.244124 dblp:conf/date/KlingaufGG06 fatcat:n7sgk74crfgibb3m4p42tvtnve

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed A. Jerraya
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems.  ...  The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity.  ...  to system programmers (HAL API) .  ... 
doi:10.1145/1120725.1120769 dblp:conf/aspdac/BouchhimaBYBJ05 fatcat:xh3b777dwrdslmkp7djxqrdi2e

A Distributed Architecture for Interacting with NAO

Fabien Badeig, Quentin Pelorson, Soraya Arias, Vincent Drouard, Israel Gebru, Xiaofei Li, Georgios Evangelidis, Radu Horaud
2015 Proceedings of the 2015 ACM on International Conference on Multimodal Interaction - ICMI '15  
An overview of the proposed software architecture is shown on Fig. 1 .  ...  The task is to detect and Overview of the proposed distributed architecture that allows fast development of interactive applications using the humanoid robot NAO.  ... 
doi:10.1145/2818346.2823303 dblp:conf/icmi/BadeigPADGLEH15 fatcat:jimhmqvbfvdgvbzsijumcye7gq

A Compositional Certification Methodology for a COTS-based system

Alvaro Ortega, Sergey Tverdyshev
2018 Zenodo  
The aim of this presentation is providing an overview of the compositional security certification methodology to be used in the scope of MILS (Multiple Independent Levels of Security) evaluations and certifications  ...  Using a MILS approach automatically enforces a partitioned architecture, which can be used to give credit to design assurance.  ...  for the partitioning of network interfaces HAL Module -Hardware abstraction layer (HAL): set of drivers for specific hardware components CPU-time Modules -CPU usage time: Period-based, Priority-based,  ... 
doi:10.5281/zenodo.3600161 fatcat:ubhxmvgzsjf6dnegi5rkuersaq

HDL Implementation of Five Moduli Residue Number System

It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.  ...  The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics.  ...  This paper compares three architectures of forward converter in RNS of five moduli using modular adders based on RCA, CSA, and HAL.  ... 
doi:10.35940/ijitee.i7768.078919 fatcat:2u6q7ijfdngc3lpfqccyakgu4i

Efficient implementation of native software simulation for MPSoC

Patrice Gerin, Xavier Guérin, Frédéric Pétrot
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Efficient and precise simulation models at a high abstraction level are required in order to perform early design validations and architecture explorations of Multi-Processor System-On-Chip (MPSoC) platforms  ...  Experimental results show the efficiency of the proposed method to validate software on complex hardware architectures.  ...  DMA transfert at TA level This DMA example gives a good overview of the TA platform to closely model hardware and software interactions capabilities.  ... 
doi:10.1145/1403375.1403540 fatcat:xd5pdvoegzevpehyzg2qwzk2fa

Analysis of 3D Structural Root Architecture Data of Trees Grown on Slopes

Fr Danjon, David H. Barker, Michael Drexhage, Alexia Stokes
2006 2006 Second International Symposium on Plant Growth Modeling and Applications  
Analysis of 3D structural root architecture data of trees grown on slopes A methodology to analyse 3D coarse root system architecture of trees grown on slope is presented in this poster.  ...  International Symposium on plant growth modelling, simulation, visualization and applications, Nov 2006, Beijing, China. 1 p. hal-02814096 Submission Form PMA06 Analysis of 3D structural root architecture  ... 
doi:10.1109/pma.2006.54 fatcat:vmu7pvkxzrfihma5uglf5amdqe

Guiding Organic Management in a Service-Oriented Real-Time Middleware Architecture [chapter]

Manuel Nickschas, Uwe Brinkschulte
2008 Lecture Notes in Computer Science  
To cope with the ever increasing complexity of today's computing systems, the concepts of organic and autonomic computing have been devised.  ...  We have already proposed a service-oriented middleware architecture for such systems that uses multi-agent principles for implementing the organic management.  ...  Overview and Motivation For an organic middleware, a service-oriented architecture proves to be a good choice.  ... 
doi:10.1007/978-3-540-87785-1_9 fatcat:cchrmyylyzhwdkrhktixzyte5y


Maxime Lorrillere, Julien Sopena, Sébastien Monnet, Pierre Sens
2015 Proceedings of the 8th ACM International Systems and Storage Conference on - SYSTOR '15  
HAL Id: hal-01154566 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published  ...  Network latency monitoring ⇒ Puma is throttled when the latency becomes too high Architecture overview PFRA alloc() VM1 VM2 P31 1 Metadata 31 P31 Reclaim 2 put(P31) 3 P31  ... 
doi:10.1145/2757667.2757669 dblp:conf/systor/LorrillereSMS15 fatcat:auio3rmgqbfyten77spc4xgowa


David Sidler, Zsolt Istvan, Muhsen Owaida, Kaan Kara, Gustavo Alonso
2017 Proceedings of the 2017 ACM International Conference on Management of Data - SIGMOD '17  
We evaluate doppioDB on an emerging hybrid multicore architecture, the Intel Xeon+FPGA platform, where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can  ...  Relational databases provide a wealth of functionality to a wide range of applications.  ...  Acknowledgments We would like to thank Intel for their generous donation of the HARP v1 prototype. Part of the work of Zsolt István has been funded by Microsoft Research.  ... 
doi:10.1145/3035918.3058746 dblp:conf/sigmod/SidlerIOKA17 fatcat:7w66bubd2zeapamrlluwr2vodq

Stroke Symbol Generation Software for Fighter Aircraft

G. Tripathi, Prashant Kumar
2013 Defence Science Journal  
This paper covers the working principle of head-up-display, overview of target hardware on which the developed software has been integrated and tested, software architecture, hardware software interfaces  ...  This paper gives an overview of the stroke symbol generation software developed by Hindustan Aeronautics Limited for fighter aircraft.  ...  HARDWARE OVERVIEW The stroke symbol generation software developed by MCSRDC, HAL has been integrated and tested on open system architecture mission computer (OSAMC) platform.  ... 
doi:10.14429/dsj.63.4257 fatcat:ahhed42i5ngphfqgs5clbnnjoe

A Multi-protocol Baseband Modem Processor for a Mobile RFID Reader [chapter]

Seok Joong Hwang, Joon Goo Lee, Seon Wook Kim, Sunshin Ahn, Si-Gyung Koo, Jihun Koo, Kyung Ho Park, Woo Shik Kang
2006 Lecture Notes in Computer Science  
We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also a chip with 0.18um technology for verification of our architecture.  ...  This paper presents architecutre of a multi-protocol RFID reader on mobile devices. We have considered several design parameters, such as low power consumption, cost effectiveness and flexibility.  ...  We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also we fabricated a chip with 0.18um technology for verification of our architecture.  ... 
doi:10.1007/11802167_79 fatcat:khku63ssuzbuxeb5ldwuwhuzru

Design and analysis of virtualization framework for Wireless Sensor Networks

Imran Khan
2013 2013 IEEE 14th International Symposium on "A World of Wireless, Mobile and Multimedia Networks" (WoWMoM)  
This paper presents the overview of the proposed WSN virtualization framework, related work, current status and future work.  ...  Each application program uses a hardware abstraction layer (HAL) to access underlying WSN resources, which means that the developer needs to be aware of the HAL, which in turn depends on the OS.  ...  INTRODUCTION Wireless Sensor Networks (WSNs) are combinations of micro-electro-mechanical systems, wireless communication systems and digital electronics nodes that sense, compute and communicate [1]  ... 
doi:10.1109/wowmom.2013.6583425 dblp:conf/wowmom/Khan13 fatcat:i6di4gukwrfshbnqbgogpssjru

Table of Contents

2020 IEEE Communications Standards Magazine  
, congchi Zhang, anD wanlu sun Survey on the Internet of Vehicles: Network Architectures and Applications Baofeng Ji, XueRu Zhang, shahiD mumtaZ, congZheng han, chunguo li, hong wen, anD Dan wang shaping  ...  S STANDARDS TANDARDS Series Editorial Vehicular Communications for ITS: Standardization and Challenges hal RoBeRts 11 26 18 34 42 43 50 10  ... 
doi:10.1109/mcomstd.2020.9088318 fatcat:y4jdxt6ezbdvtpreqmaossgqya

Sistem Informasi Penjualan Mobil Berbasis Web dengan Memanfaatkan Metode Visual Architecting ProcessTM (Studi Kasus : CV. Cahaya Mobilindo)

Hendra Di Kesuma
2019 Jurnal Ilmiah Informatika Global  
Moreover, validation of the architecture can be done at the same time to ensure that the architects and stakeholders agree that the chosen architecture is the most appropriate.  ...  <p align="center"><strong>Abstract</strong></p><p>This research explores how architectural needs can be analysed and priorities determined to create the right architecture.  ...  System Structuring (Architectural Specification) System Structuring merupakan tahapan yang bertujuan untuk merancang struktur sebagai panduan bagi pengembangan atau implementasi.  ... 
doi:10.36982/jig.v9i2.582 fatcat:5mozqyyzhzewveab5b4dicrrwa
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